EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 147

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

DS785UM1
Note: The value in the register is the actual coefficient minus one.
Note: The value in the register is the actual coefficient minus one.
Note: This means that PLL2 FOUT is programmed to be 48,000,000 Hz on startup.
Note: The value in the register is the actual coefficient minus one.
PLL2_X2FBD2:
PLL2_X1FBD1:
PLL2_PS:
PLL2_EN:
nBYP2:
USBDIV:
Copyright 2007 Cirrus Logic
These 6 register bits set the first feedback divider bits for
PLL2. On power-on-reset the value is set to 11000b (24
decimal).
These 5 register bits set the second feedback divider bits
for PLL2. On power-on-reset the value is set to 11000b (24
decimal).
These two bits determine the final divide function on the
VCO clock signal in PLL2.
00 - Divide by 1
01 - Divide by 2
10 - Divide by 4
11 - Divide by 8
On power-on-reset these bits are reset to 11b (3 decimal).
This bit enables PLL2. If set, PLL2 is enabled. If this bit is
zero, PLL2 is disabled. On power-on-reset the value is set
to 0b.
This bit selects the clock source for the processor clock
dividers. If set, PLL2 is the clock source. If this bit is set to
zero, the external clock is the clock source. On power-on-
reset, this bit defaults to 0b.
These four bits set the divide ratio between the PLL2
output and the USB clock.
0000 - Divide by 1
0001 - Divide by 2
0010 - Divide by 3
0011 - Divide by 4
0100 - Divide by 5
0101 - Divide by 6
0110 - Divide by 7
0111 - Divide by 8
On power-on-reset these bits are reset to 0000b.
1111 - Divide by 1
1011 - Divide by 12
1110 - Divide by 15
1000 - Divide by 9
1001 - Divide by 10
1010 - Divide by 11
1100 - Divide by 13
1101 - Divide by 14
EP93xx User’s Guide
System Controller
5-21
5