EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 224

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

7
Horizontal Frame Timing Registers
HClkTotal
HSyncStrtStop
7-42
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
31
15
Address: 0x8003_0010
Default: 0x0000_0000
Definition: Total pixel clocks that compose a horizontal line
Bit Descriptions:
Address: 0x8003_0014
Default: 0x0000_0000
Definition: HorizontaL Sync Start/Stop Register
Bit Descriptions:
30
14
30
14
RSVD
RSVD
RSVD
29
13
29
13
28
12
28
12
RSVD:
TOTAL:
RSVD:
STOP:
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved - Unknown during read
Total - Read/Write
The HClk Total timing register contains the total number of
clocks for a horizontal video line including synchronization,
blanking, and active clocks. This value is used to preset
the Horizontal down counter. Please refer to video
signalling timing diagrams in
Reserved - Unknown during read
Stop - Read/Write
24
24
8
8
RSVD
23
23
7
7
22
22
6
6
TOTAL
STOP
STRT
21
21
5
5
Figure 7-9
20
20
4
4
19
19
3
3
and
18
18
2
2
Figure
17
17
1
1
DS785UM1
7-10.
16
16
0
0