MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 91

• Manufacturer Part Number: MC9S08DZ60ACLF
• Description: IC MCU 60K FLASH 4K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ60ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• For Use With: DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6
The MC9S08DZ128 Series includes a system to protect against low-voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and
detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon
entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then
the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the
LVD enabled will be higher.
5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, V
LVD circuit will hold the MCU in reset until the supply has risen above the low-voltage detection low
threshold, V
5.6.2
The LVD can be configured to generate a reset upon detection of a low-voltage condition by setting
LVDRE to 1. The low-voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the
low-voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or
POR.
Freescale Semiconductor
1
Number
Vector
Vector priority is shown from lowest (first row) to highest (last row). For example, Vreset is the highest priority vector.
6
5
4
3
2
1
0
Low-Voltage Detect (LVD) System
Power-On Reset Operation
Low-Voltage Detection (LVD) Reset Operation
LVDL
0xFFF2/0xFFF3
0xFFF4/0xFFF5
0xFFF6/0xFFF7
0xFFF8/0xFFF9
0xFFFA/0xFFFB
0xFFFC/0xFFFD
0xFFFE/0xFFFF
(High/Low)
Address
. Both the POR bit and the LVD bit in SRS are set following a POR.
POR
, the POR circuit will cause a reset condition. As the supply voltage rises, the
Vtpm1ch1
Vtpm1ch0
Vector
Vreset
Name
Vswi
Vlvd
Virq
Vlol
MC9S08DZ128 Series Data Sheet, Rev. 1
Table 5-1. Vector Summary
Module
System
System
control
control
TPM1
TPM1
MCG
Core
IRQ
SWI Instruction
RESET,
Source
LVWF
BDFR
CH1F
CH0F
LOLS
IRQF
ILOP,
ILAD,
POR,
COP,
LOC,
LVD,
Chapter 5 Resets, Interrupts, and General System Control
1
Enable
LVDRE
CH1IE
CH0IE
LVWIE
LOLIE
COPT
IRQIE
CME
—
—
—
—
—
—
TPM1 channel 1
TPM1 channel 0
MCG loss of lock
Low-voltage warning
IRQ pin
Software interrupt
Watchdog timer
Loss-of-clock
Low-voltage detect
External pin
Illegal opcode
Illegal address
Power-on-reset
BDM-forced reset
Description
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