MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 407

• Manufacturer Part Number: MC9S08DZ60ACLF
• Description: IC MCU 60K FLASH 4K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ60ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• For Use With: DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.3.14 Debug Trigger Register (DBGT)
1
2
Freescale Semiconductor
end-run
Module Base + 0x000D
The DBG trigger register (DBGT) can not be changed unless ARM=0.
end-run
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the control bits in this register do not change after reset.
TRGSEL
Reset
BEGIN
Field
POR
TRG
3–0
W
7
6
R
2
1
TRGSEL
Trigger Selection Bit — The TRGSEL bit controls the triggering condition for the comparators. See
Section 18.4.4, “Trigger Break Control (TBC)”
0 Trigger on any compare address access
1 Trigger if opcode at compare address is executed
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO.
0 Trigger at end of stored data
1 Trigger before storing data
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown in
U
0
7
= Unimplemented or Reserved
BEGIN
U
1
6
Figure 18-15. Debug Trigger Register (DBGT)
TRG Value
Table 18-16. DBGT Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
Table 18-17. Trigger Mode Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
0
0
0
5
A And Not B (Full mode)
0
0
0
4
for more information.
A Then Event Only B
A And B (Full Mode)
Description
Outside Range
Event Only B
Inside Range
A Then B
Meaning
A Only
A Or B
U
0
3
Chapter 18 Debug Module (S08DBGV3) (128K)
U
0
2
TRG
U
0
1
Table
18-17.
U
0
0
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