C8051F988-GM Silicon Laboratories Inc, C8051F988-GM Datasheet - Page 183
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C8051F988-GM
Manufacturer Part Number
C8051F988-GM
Description
IC MCU 8BIT 4KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F988-GM
Program Memory Type
FLASH
Program Memory Size
4KB (4K x 8)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1959-5
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this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The missing clock detector reset is automatically disabled when the device is in the low power suspend or
sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is
restored to its previous value. The state of the RST pin is unaffected by this reset.
18.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The Comparator0 reset source remains
functional even when the device is in the low power suspend and sleep states as long as Comparator0 is
also enabled as a wake-up source. The state of the RST pin is unaffected by this reset.
18.6. PCA Watchdog Timer Reset
The programmable watchdog timer (WDT) function of the programmable counter array (PCA) can be used
to prevent software from running out of control during a system malfunction. The PCA WDT function can
be enabled or disabled by software as described in Section “26.4. Watchdog Timer Mode” on page 309;
the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction prevents
user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to 1.
The PCA Watchdog Timer reset source is automatically disabled when the device is in the low power
suspend or sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset
source is restored to its previous value.The state of the RST pin is unaffected by this reset.
18.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
18.8. SmaRTClock (Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or
SmaRTClock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock
Detector is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm
event occurs when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the
ALARMn registers. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE
flag (RSTSRC.7). The SmaRTClock reset remains functional even when the device is in the low power
Suspend or Sleep mode. The state of the RST pin is unaffected by this reset.
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“14.3. Security Options” on page 151).
A Flash write or erase is attempted while the V
Rev. 1.0
DD
Monitor is disabled.
C8051F99x-C8051F98x
183
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