ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 98

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

On-chip peripherals
Note:
10.4.3
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In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
General description
Figure 49
registers:
●
●
●
The SPI is connected to external devices through four pins:
●
●
●
●
Figure 48. Serial peripheral interface block diagram
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
MOSI
MISO
SCK
SS
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
MISO: Master In / Slave Out data
MOSI: Master Out / Slave In data
SCK: Serial Clock out by SPI masters and input by SPI slaves
SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines. Slave
SS inputs can be driven by standard I/O ports on the master MCU.
shows the serial peripheral interface (SPI) block diagram. The SPI has three
SOD
Figure
bit
SPIDR
49.
8-bit Shift Register
Read Buffer
Doc ID13466 Rev 4
Serial clock
generator
Master
control
Data/Address bus
Read
Write
7
SPIF WCOL
SPIE SPE
7
SPR2
OVR
control
state
SPI
Interrupt
request
MODF
MSTR
CPOL
0
ST72324B-Auto
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
1
0
SPR0
SSI
0
0