ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 46

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

Interrupts
7.5.2
Caution:
46/198
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see
Interrupt software priority registers (ISPRx)
These four registers contain the interrupt software priority of each interrupt vector.
●
Table 17.
●
●
The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 18.
ISPRx
HALT
Instruction
ISPR0
ISPR1
ISPR2
ISPR3
Each interrupt vector (except reset and TRAP) has corresponding bits in these
registers where its own software priority is stored. This correspondence is shown in the
following
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1
and I0 bits in the CC register.
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value
is kept (for example, previous value = CFh, write = 64h, result = 44h).
I1_11
Entering HALT mode
ISPRx interrupt vector correspondence
Dedicated interrupt instruction set
Vector address
I1_3
I1_7
R/W
RO
FFFBh-FFFAh
FFE1h-FFE0h
FFF9h-FFF8h
Table
7
1
New description
...
17.
I0_11
I0_3
I0_7
R/W
RO
6
1
Table 18: Dedicated interrupt instruction
Doc ID13466 Rev 4
I1_10
I1_2
I1_6
R/W
RO
5
1
Function/example
I0_10
R/W
I0_2
I0_6
RO
4
1
(1)
I1_13
I1_1
I1_5
I1_9
R/W
R/W
3
I1_13 and I0_13 bits
I1_0 and I0_0 bits
I1_1 and I0_1 bits
ISPRx bits
I1
1
I0_13
Reset value: 1111 1111 (FFh)
I0_1
I0_5
I0_9
R/W
R/W
...
2
H
set).
I0
0
I1_12
I1_8
R/W
R/W
I1_0
I1_4
ST72324B-Auto
1
N
Z
I0_12
I0_0
I0_4
I0_8
R/W
R/W
0
C