ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 21

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
Table 3.
1. Legend: x = undefined, R/W = read/write.
2. The bits associated with unavailable pins must always keep their reset value.
3. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
Address
0058h to
004Ah
004Bh
004Ch
004Dh
004Eh
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
006Fh
0070h
0071h
0072h
0073h
007Fh
I/O pins are returned instead of the DR register contents.
Timer B
Hardware register map (continued)
Block
ADC
SCI
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR

SCIETPR
ADCCSR
ADCDRH
ADCDRL
Register label
Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
Timer B counter low register
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register
SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
SCI extended transmit prescaler register
Control/status register
Data high register
Data low register
Doc ID13466 Rev 4
Reserved area (24 bytes)
Reserved area (13 bytes)
Register name
Register and memory map
x000 0000b
xxxx x0xxb
status
Reset
FFh
FCh
FFh
FCh
C0h
00h
00h
xxh
xxh
80h
00h
xxh
xxh
80h
00h
xxh
00h
00h
00h
00h
00h
00h
00h
---
(1)
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
Read only
R/W
R/W
R/W
R/W
R/W

R/W
R/W
Read only
Read only
Remarks
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