ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 75

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
10.3.3
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
●
●
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and
PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table
clock cycles depending on the CC[1:0] bits. The timer frequency can be f
f
CPU
/8 or an external frequency.
Counter Register (CR)
–
–
Alternate Counter Register (ACR)
–
–
50. The value in the counter register repeats every 131072, 262144 or 524288 CPU
Counter High Register (CHR) is the most significant byte (MSB)
Counter Low Register (CLR) is the least significant byte (LSB)
Alternate Counter High Register (ACHR) is the most significant byte (MSB)
Alternate Counter Low Register (ACLR) is the least significant byte (LSB)
Doc ID13466 Rev 4
16-bit read
On-chip peripherals
CPU
sequence).
/2, f
CPU
/4,
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