ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 128

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

On-chip peripherals
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Table 65.
SCI Extended Receive Prescaler Division Register (SCIERPR)
This register is used to set the Extended Prescaler rate division factor for the receive circuit.
Table 66.
SCI Extended Transmit Prescaler Division Register (SCIETPR)
This register is used to set the External Prescaler rate division factor for the transmit circuit.
SCIERPR
5:3 SCT[2:0]
2:0 SCR[2:0]
7:0
Bit
Bit
7
ERPR[7:0]
Name
Name
SCIBRR register description (continued)
SCIERPR register description
SCI Transmitter rate divisor
SCI Receiver rate divisor
6
These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division
applied to the bus clock to yield the transmit rate clock in conventional baud rate
generator mode. 
000: TR dividing factor = 1
001: TR dividing factor = 2
010: TR dividing factor = 4
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
111: TR dividing factor = 128
These 3 bits, in conjunction with the SCP[1:0] bits, define the total division applied
to the bus clock to yield the receive rate clock in conventional baud rate generator
mode.
000: RR dividing factor = 1
001: RR dividing factor = 2
010: RR dividing factor = 4
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
8-bit Extended Receive Prescaler Register
The extended baud rate generator is activated when a value different from 00h
is stored in this register. Therefore the clock frequency issued from the 16
divider (see
register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
5
Doc ID13466 Rev 4
Figure
57) is divided by the binary factor set in the SCIERPR
4
ERPR[7:0]
R/W
Function
Function
3
2
Reset value: 0000 0000 (00h)
1
ST72324B-Auto
0