LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 712

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
4. Functional overview
UM10237_4
User manual
4.1 Memory regions accessible by the GPDMA
4.2 GPDMA functional description
This chapter describes the major functional blocks of the GPDMA. It contains the following
sections:
Table 649. GPDMA accessible memory
[1]
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
Memory region
On-chip RAM
Off-Chip Memory
•
•
•
•
•
•
•
•
•
•
•
Supports 8, 16, and 32 bit wide transactions.
Big-endian and little-endian support. The GPDMA defaults to little-endian mode on
reset.
An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
Interrupt masking. The DMA error and DMA terminal count interrupt requests can be
masked.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
Test registers for use in block and integration system level testing.
Identification registers that uniquely identify the GPDMA. These can be used by an
operating system to automatically configure itself.
GPDMA functional description
System considerations
System connectivity
Use with memory management unit based systems
For LPC2458, see
Table
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
2–14.
Address range
0x7FD0 0000 - 0x7FD0 3FFF
Four static memory banks, 16 MB each
0x8000 0000 - 0x80FF FFFF
0x8100 0000 - 0x81FF FFFF
0x8200 0000 - 0x82FF FFFF
0x8300 0000 - 0x83FF FFFF
Four dynamic memory banks, 256 MB each
0xA000 0000 - 0xAFFF FFFF
0xB000 0000 - 0xBFFF FFFF
0xC000 0000 - 0xCFFF FFFF
0xD000 0000 - 0xDFFF FFFF
[1]
Memory Type
USB RAM (16 kB)
Static memory bank 0
Static memory bank 1
Static memory bank 2
Static memory bank 3
Dynamic memory bank 0
Dynamic memory bank 1
Dynamic memory bank 2
Dynamic memory bank 3
UM10237
© NXP B.V. 2009. All rights reserved.
712 of 792