LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 49
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
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UM10237_4
User manual
3.2.5 PLL Configuration register (PLLCFG - 0xE01F C084)
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see
0xE01F
Table 44.
The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is locked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (see
Section 4–3.2.9 “PLL Feed register (PLLFEED - 0xE01F
PLL frequency, and multiplier and divider values are found in the
frequency
Table 45.
Bit
0
1
7:2
Bit
14:0
15
23:16 NSEL
31:24 -
Symbol
PLLE
PLLC
-
Symbol
MSEL
-
C08C)”).
calculation”.
PLL Control register (PLLCON - address 0xE01F C080) bit description
PLL Configuration register (PLLCFG - address 0xE01F C084) bit description
Description
PLL Enable. When one, and after a valid PLL feed, this bit will
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register,
PLL Connect. Having both PLLC and PLLE set to one followed by a
valid PLL feed sequence, the PLL becomes the clock source for the
CPU, as well as the USB subsystem and. Otherwise, the clock
selected by the Clock Source Selection Multiplexer is used directly
by the LPC2400. See PLLSTAT register,
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
PLL Multiplier value. Supplies the value "M" in the PLL frequency
calculations. The value stored here is M - 1. Supported values for M
are 6 through 512 and those listed in
Note: Not all values of M are needed, and therefore some are not
supported by hardware. For details on selecting values for MSEL see
Section 4–3.2.11 “PLL frequency
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
PLL Pre-Divider value. Supplies the value "N" in the PLL frequency
calculations. PLL Pre-Divider value. Supplies the value "N" in the PLL
frequency calculations. Supported values for N are 1 through 32.
Note: For details on selecting the right value for NSEL see
4–3.2.11 “PLL frequency
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Section 4–3.2.9 “PLL Feed register (PLLFEED -
Table
Chapter 4: LPC24XX Clocking and power control
4–47.
calculation”.
calculation”.
Table
Table
C08C)”). Calculations for the
4–46.
4–47.
Section 4–3.2.11 “PLL
UM10237
© NXP B.V. 2009. All rights reserved.
Section
Reset
value
0
0
NA
49 of 792
Reset
value
0
NA
0
NA
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