LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 420

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
Fig 64. Clocking and power control
USB CLOCK
DIVIDER
PCUSB
cclk
usbclk
(48 MHz)
9.1 Device clock request signals
The Device controller has two clock request signals, dev_need_clk and
dev_dma_need_clk. When asserted, these signals turn on the device’s 48 MHz clock and
ahb_master_clk respectively.
The dev_need_clk signal is asserted while the device is not in the suspend state, or if the
device is in the suspend state and activity is detected on the USB bus. The dev_need_clk
signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device
Status register –
normal operation when software does not need to access the Device controller registers –
the Device will continue to function normally and automatically shut off its clock when it is
suspended or disconnected.
EN
EN
EN
EN
EN
SWITCH
SWITCH
SWITCH
SWITCH
SWITCH
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
ahb_master_clk
ahb_slave_clk
AHB_CLK_ON
DEV_CLK_ON
HOST_CLK_ON
OTG_CLK_ON
I2C_CLK_ON
Section
Rev. 04 — 26 August 2009
13–11). This signal allows DEV_CLK_EN to be cleared during
CONTROLLER
CONTROLLER
CONTROLLER
CONTROLLER
INTERFACE
REGISTER
DEVICE
HOST
HOST_CLK_EN
OTG
I2C
DEV_CLK_EN
OTG_CLK_EN
AHB_CLK_EN
I2C_CLK_EN
Chapter 15: LPC24XX USB OTG controller
dev_dma_need_clk
dev_need_clk
host_dma_need_clk
host_need_clk
ahb_need_clk
UM10237
© NXP B.V. 2009. All rights reserved.
USB_NEED_CLK
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