LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 632
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
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Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
Exar
Quantity:
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Part Number:
LPC2470FET208,551
Manufacturer:
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1. Basic configuration
2. Features
UM10237_4
User manual
The PWM is configured using the following registers:
1. Power: In the PCONP register
2. Peripheral clock: In the PCLK_SEL0 register
3. Pins: Select PWM pins and pin modes in registers PINSELn and PINMODEn (see
4. Interrupts: See register PWM0/1MCR
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UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Rev. 04 — 26 August 2009
Remark: On reset, the both PWMs are enabled (PCPWM0/1 = 1).
Section
(Table
the VICIntEnable register
Two PWMs with the same operational features. The PWMs may be operated in a
synchronized fashion by setting them both up to run at the same rate, then enabling
both simultaneously. PWM0 acts as the Master and PWM1 as the slave for this use.
Counter or Timer operation (may use the peripheral clock or one of the capture inputs
as the clock source).
Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must "release" new match values before they can
become effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
Three 32 bit capture channels take a snapshot of the timer value when an input signal
transitions. A capture event may also optionally generate an interrupt.
25–561) for match and capture events. Interrupts are enabled in the VIC using
9–5).
Rev. 04 — 26 August 2009
(Table
(Table
7–106).
4–63), set bit PCPWM0/1.
(Table
25–560) and PWM0/1CCR
(Table
4–56), select PCLK_PWM0/1.
© NXP B.V. 2009. All rights reserved.
User manual
632 of 792
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