LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 322

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
7.25 Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1
7.26 Cursor Masked Interrupt Status register (CRSR_INTSTAT, RW -
0C28)
The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the
CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt
controller.
The contents of the CRSR_INTRAW register are described in
Table 284. Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1 0C28)
0xFFE1 0C2C)
The CRSR_INTSTAT register is set to indicate a cursor interrupt providing that the
interrupt is not masked in the
The contents of the CRSR_INTSTAT register are described in
Table 285. Cursor Masked Interrupt Status register (CRSR_INTSTAT, RW - 0xFFE1 0C2C)
Bits
31:1
0
Bits
31:1
0
Function
reserved
CrsrRIS
Function
reserved
CrsrMIS
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Cursor raw interrupt status.
The cursor interrupt status is set immediately after the last data
is read from the cursor image for the current frame.
This bit is cleared by writing to the CrsrIC bit in the
CRSR_INTCLR register.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Cursor masked interrupt status.
The cursor interrupt status is set immediately after the last data
read from the cursor image for the current frame, providing that
the corresponding bit in the CRSR_INTMSK register is set.
The bit remains clear if the CRSR_INTMSK register is clear.
This bit is cleared by writing to the CRSR_INTCLR register.
CRSR_INTMSK
register.
Chapter 12: LPC24XX LCD controller
Table
Table
12–284.
12–285.
UM10237
© NXP B.V. 2009. All rights reserved.
322 of 792
Reset
value
-
0x0
Reset
value
-
0x0