LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 481
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
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Quantity
Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
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Quantity:
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Part Number:
LPC2470FET208,551
Manufacturer:
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UM10237_4
User manual
Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in
CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either
of these bytes is captured, its value will remain the same until it is read, at which time it is
released to capture a new value.
The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read
from CANxICR, regardless of whether part or all of the register is read. This means that
software should always read CANxICR as a word, and process and deal with all bits of the
register as appropriate for the application.
Table 423. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR -
Bit
0
1
2
3
4
5
6
7
Symbol
RI
TI1
EI
DOI
WUI
EPI
ALI
BEI
[1]
address 0xE004 800C) bit description
[2]
Value
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
0 (reset)
1 (set)
Rev. 04 — 26 August 2009
Function
Receive Interrupt. This bit is set whenever the RBS bit
in CANxSR and the RIE bit in CANxIER are both 1,
indicating that a new message was received and
stored in the Receive Buffer.
Transmit Interrupt 1. This bit is set when the TBS1 bit
in CANxSR goes from 0 to 1 (whenever a message
out of TXB1 was successfully transmitted or aborted),
indicating that Transmit buffer 1 is available, and the
TIE1 bit in CANxIER is 1.
Error Warning Interrupt. This bit is set on every
change (set or clear) of either the Error Status or Bus
Status bit in CANxSR and the EIE bit bit is set within
the Interrupt Enable Register at the time of the
change.
Data Overrun Interrupt. This bit is set when the DOS
bit in CANxSR goes from 0 to 1 and the DOIE bit in
CANxIER is 1.
Wake-Up Interrupt. This bit is set if the CAN controller
is sleeping and bus activity is detected and the WUIE
bit in CANxIER is 1.
Error Passive Interrupt. This bit is set if the EPIE bit in
CANxIER is 1, and the CAN controller switches
between Error Passive and Error Active mode in
either direction.
This is the case when the CAN Controller has reached
the Error Passive Status (at least one error counter
exceeds the CAN protocol defined level of 127) or if
the CAN Controller is in Error Passive Status and
enters the Error Active Status again.
Arbitration Lost Interrupt. This bit is set if the ALIE bit
in CANxIER is 1, and the CAN controller loses
arbitration while attempting to transmit. In this case
the CAN node becomes a receiver.
Bus Error Interrupt -- this bit is set if the BEIE bit in
CANxIER is 1, and the CAN controller detects an error
on the bus.
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
0
0
0
0
0
0
0
0
481 of 792
RM
Set
0
0
X
0
0
0
0
X
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