LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 32
![IC ARM7 MCU LCD 208-TFBGA](/photos/12/13/121398/lpc2470fet208-s_sml.jpg)
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
Exar
Quantity:
92
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
On the assertion of any of reset sources (POR, BOD reset, External reset and Watchdog
reset), the following two sequences start simultaneously:
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 3–11
processor status when the LPC2400 starts up after reset. For the start-up sequence of the
main oscillator if enabled by the user code, see
USB need_clk wakeup
1. After IRC-start-up time (maximum of 60 μs on power-up), IRC provides stable clock
2. After IRC-start-up time (maximum of 60 μs on power-up), IRC provides stable clock
Ethernet MAC wakeup
Fig 10. Reset block diagram including the wakeup timer
GPIO0 port wakeup
GPIO2 port wakeup
output, the reset signal is latched and synchronized on the IRC clock. The 2-bit IRC
wakeup timer starts counting when the synchronized reset is de-asserted. The boot
code in the ROM starts when the 2-bit IRC wakeup timer times out. The boot code
performs the boot tasks and may jump to the flash. If the flash is not ready to access,
the MAM will insert wait cycles until the flash is ready.
output, the reset signal is synchronized on the IRC clock. The flash wakeup-timer
(9-bit) starts counting when the synchronized reset is de-asserted. The flash
wakeup-timer generates the 100 μs flash start-up time. Once it times out, the flash
initialization sequence is started, which takes about 250 cycles. When it’s done, the
MAM will be granted access to the flash.
external
reset
EINT0 wakeup
EINT1 wakeup
EINT2 wakeup
EINT3 wakeup
watchdog
CAN wakeup
power-
BOD wakeup
RTC wakeup
down
reset
POR
BOD
shows an example of the relationship between the RESET, the IRC, and the
Rev. 04 — 26 August 2009
C
S
Q
internal RC
oscillator
Section 4–2.2 “Main
Chapter 3: LPC24XX System control
from APB
write “1”
START
WAKEUP TIMER
reset
COUNT 2
Reset to the
on-chip circuitry
Reset to
PCON.PD
oscillator”.
UM10237
n
© NXP B.V. 2009. All rights reserved.
APB read of
PDBIT
in PCON
F
to other
blocks
OSC
C
S
32 of 792
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