P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 81

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
15.2.12 T
The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the SIO1 hardware:
the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the
I
Table 55 Address Register S1CON (address D8H)
Table 56 Description of S1CON (D8H) bits
2000 Jul 26
2
C bus. The STO bit is also cleared when ENS1 = 0.
BIT
Single-chip 8-bit microcontroller with CAN controller
7
6
5
4
3
2
1
0
CR2
7
SYMBOL
HE
ENS1
CR2
STO
CR1
CR0
STA
AA
C
SI
ONTROL
ENS1
6
Clock rate bit 2, see Table 57.
Enable serial I/O. ENS1 = 0: I
START flag. When this bit is set in slave mode, the hardware checks the I
a START condition if the bus is free or after the bus becomes free. If the device operates in
master mode it will generate a repeated START condition.
STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition
detected on the I
from an error condition. In this case no STOP condition is generated to the I
hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The
STOP flag is cleared by the hardware.
Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the
following events occur:
While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset
by software.
Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the
following conditions:
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when
the own address or general call address is received.
Clock rate bits 1 and 0; see Table 57.
R
A START condition is generated in master mode.
The own slave address has been received during AA = 1.
The general call address has been received while S1ADR.0 and AA = 1.
A data byte has been received or transmitted in master mode (even if arbitration is lost).
A data byte has been received or transmitted as selected slave.
A STOP or START condition is received as selected slave receiver or transmitter.
Own slave address is received.
General call address is received (S1ADR.0 = 1).
A data byte is received, while the device is programmed to be a master receiver.
A data byte is received. while the device is a selected slave receiver.
EGISTER
, S1CON
STA
5
2
C-bus clears this bit. This bit may also be set in slave mode in order to recover
STO
4
2
C I/O disabled and reset. ENS1 = 1: serial I/O enabled.
81
DESCRIPTION
SI
3
AA
2
Preliminary Specification
CR1
2
1
C-bus and generates
2
C-bus, but the
P8xC591
CR0
0