P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 37

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
Notes to Table 15:
1. When the Transmit Error Counter exceeds the limit of 255, the Bus Status bit is set ‘1’ (Bus-Off), the CAN controller
2. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The
3. If both the Receive Status and the Transmit Status bits are ‘0’ (idle) the CAN-Bus is idle.
4. The Transmission Complete Status bit is set ‘0’ (incomplete) whenever the Transmission Request bit or the Self
5. If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Status bit is ‘0’ (locked), the written byte will
6. When a message that is to be received has passed the acceptance filter successfully, the CAN controller needs
7. After reading all messages within the RXFIFO and releasing their memory space with the command Release Receive
2000 Jul 26
Single-chip 8-bit microcontroller with CAN controller
will set the Reset Mode bit ‘1’ (present), an Error Warning and a Bus Error Interrupt is generated, if enabled. The
Transmit Error Counter is set to ‘127’. It will stay in this mode until the CPU clears the Reset Request bit. Once this
is completed the CAN controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal)
counting down the Transmit Error Counter. After that the Bus Status bit is cleared (Bus-On), the Error Status bit is
set ‘0’ (ok), the Error Counters are reset and an Error Interrupt is generated, if enabled. Reading the TX Error Counter
during this time gives information about the status of the Bus-Off recovery.
Error Status bit is set when at least one of the error counters has reached or exceeded the CPU warning limit of 96.
An Error Interrupt is generated, if enabled.
Reception Request bit is set ‘1’. The Transmission Complete Status bit will remain ‘0’ until a message is transmitted
successfully.
not be accepted and will be lost without this being signalled.
space in the RXFIFO to store the message descriptor and for each data byte which has been received. If there is not
enough space to store the massage, that message is dropped and the data overrun condition is indicated to the CPU
at the moment this message becomes valid. If this message is not completed (e.g. because of an error), no overrun
condition is indicated.
Buffer this bit is cleared.
37
Preliminary Specification
P8xC591