PIC18C442-I/P Microchip Technology, PIC18C442-I/P Datasheet - Page 28

• Manufacturer Part Number: PIC18C442-I/P
• Description: IC MCU OTP 8KX16 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
3.1
A Power-on Reset pulse is generated on-chip when
V
cuitry, just tie the MCLR pin directly (or through a resis-
tor) to V
usually needed to create a Power-on Reset delay. A
minimum rise rate for V
D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in reset until the operating condi-
tions are met.
FIGURE 3-2:
3.2
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows V
able level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to V
parameter #33 for details.
DS39026C-page 26
DD
Note 1: External Power-on Reset circuit is required
DD
rise is detected. To take advantage of the POR cir-
, temperature and process variation. See DC
DD
Power-on Reset (POR)
Power-up Timer (PWRT)
2: R < 40 k is recommended to make sure that
3: R1 = 100
. This will eliminate external RC components
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
ing into MCLR from external capacitor C in
the event of MCLR/V
to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
V
DD
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
to 1 k will limit any current flow-
DD
DD
DD
R1
power-up slope is too slow.
powers down.
is specified (parameter
DD
PP
DD
PIC18CXXX
MCLR
pin breakdown, due
to rise to an accept-
POWER-UP)
3.3
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(T
up time-out (OST).
3.5
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If V
than parameter #35, the brown-out situation will reset
the chip. A RESET may not occur if V
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until V
BV
will keep the chip in RESET an additional time delay
(parameter #33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once V
will execute the additional time delay.
3.6
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18CXXX device oper-
ating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all the registers.
PLL
DD
) is typically 2 ms and follows the oscillator start-
. The Power-up Timer will then be invoked and
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
Time-out Sequence
DD
DD
falls below parameter D005 for greater
rises above BV
DD
drops below BV
2001 Microchip Technology Inc.
DD
, the Power-up Timer
DD
DD
DD
rises above
falls below
while the