PIC18C442-I/P Microchip Technology, PIC18C442-I/P Datasheet - Page 145

• Manufacturer Part Number: PIC18C442-I/P
• Description: IC MCU OTP 8KX16 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

FIGURE 14-21:
14.4.12
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condi-
tion, de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 14-22).
FIGURE 14-22:
BRG overflow,
Release SCL,
If SCL = 1, Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
2001 Microchip Technology Inc.
SCL
SDA
CLOCK ARBITRATION
Note: T
SCL
SDA
Falling edge of
9th clock
Write to SSPCON2
BRG
STOP CONDITION RECEIVE OR TRANSMIT MODE
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
= one baud rate generator period.
ACK
Set PEN
T
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to setup STOP condition.
T
BRG
T
SCL brought high after T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
P
SCL = 1 for Tbrg, followed by SDA = 1 for Tbrg
after SDA sampled high. P bit (SSPSTAT<4>) is set
T
BRG
14.4.13
While in SLEEP mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
14.4.14
A RESET disables the MSSP module and terminates
the current transfer.
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
BRG
SLEEP OPERATION
EFFECT OF A RESET
T
SCL = 1 BRG starts counting
clock high interval.
BRG
PIC18CXX2
2
C module can receive
OSC
DS39026C-page 143
² 4).