PIC18C442-I/P Microchip Technology, PIC18C442-I/P Datasheet - Page 136

• Manufacturer Part Number: PIC18C442-I/P
• Description: IC MCU OTP 8KX16 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
14.4.4
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
1.
2.
3.
4.
5.
6.
FIGURE 14-13:
DS39026C-page 134
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA
and SCL.
Write to the SSPBUF register initiating transmis-
sion of data/address.
Generate a STOP condition on SDA and SCL.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
SDA
SCL
I
2
C MASTER MODE SUPPORT
2
C port to receive data.
MSSP BLOCK DIAGRAM (I
SDA in
Bus Collision
SCL in
Read
MSb
Write Collision Detect
START bit, STOP bit,
START bit Detect
end of XMIT/RCV
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
SSPSR
Generate
2
C MASTER MODE)
LSb
Write
Clock
Data Bus
Shift
Note:
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
The MSSP module, when configured in I
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2001 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
2
C