PIC18C442-I/P Microchip Technology, PIC18C442-I/P Datasheet - Page 195

• Manufacturer Part Number: PIC18C442-I/P
• Description: IC MCU OTP 8KX16 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.1
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
Instruction Set
WREG = 0x10
WREG = 0x25
Q1
ADD literal to WREG
[ label ] ADDLW
0
(WREG) + k
N,OV, C, DC, Z
The contents of WREG are added
to the 8-bit literal ’k’ and the result is
placed in WREG.
1
1
literal ’k’
ADDLW
Read
0000
Q2
k
255
0x15
1111
Process
Data
Q3
WREG
k
kkkk
Write to
WREG
Q4
kkkk
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WREG
REG
WREG
REG
Q1
=
=
=
=
register ’f’
ADD WREG to f
[ label ] ADDWF
0
d
a
(WREG) + (f)
N,OV, C, DC, Z
Add WREG to register ’f’. If ’d’ is 0,
the result is stored in WREG. If ’d’
is 1, the result is stored back in reg-
ister 'f' (default). If ‘a’ is 0, the
Access Bank will be selected. If ‘a’
is 1, the BSR is used.
1
1
ADDWF
Read
0010
Q2
0x17
0xC2
0xD9
0xC2
f
[0,1]
[0,1]
PIC18CXX2
255
01da
REG, 0, 0
Process
Data
Q3
DS39026C-page 193
dest
ffff
f [,d [,a] f [,d [,a]
destination
Write to
Q4
ffff