PIC18C442-I/P Microchip Technology, PIC18C442-I/P Datasheet - Page 259

• Manufacturer Part Number: PIC18C442-I/P
• Description: IC MCU OTP 8KX16 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

FIGURE 21-17:
TABLE 21-16: I
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
Param.
2001 Microchip Technology Inc.
No.
2: A fast mode I
T
T
T
T
T
T
T
T
T
T
T
C
SDA
Out
Note:
SDA
In
SCL
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
T
released.
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
Symbol
B
R
:
:
:
:
:
STA
DAT
STO
max. + T
STA
DAT
Refer to Figure 21-4 for load conditions.
2
C BUS DATA REQUIREMENTS (SLAVE MODE)
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
SU
2
I
C bus device can be used in a standard mode I
:
2
DAT
90
C BUS DATA TIMING
103
= 1000 + 250 = 1250 ns (according to the standard mode I
91
Characteristic
109
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
SSP Module
SSP Module
100
106
101
109
20 + 0.1C
20 + 0.1C
1.5T
1.5T
107
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
2
C bus system, but the requirement T
CY
CY
B
B
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification) before the SCL line is
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
PIC18CXX2
PIC18CXXX must operate at a
minimum of 1.5 MHz
PIC18CXXX must operate at a
minimum of 10 MHz
PIC18CXXX must operate at a
minimum of 1.5 MHz
PIC18CXXX must operate at a
minimum of 10 MHz
C
10 to 400 pF
C
10 to 400 pF
Only relevant for Repeated
START condition
After this period the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free before
a new transmission can start
92
B
B
is specified to be from
is specified to be from
102
110
Conditions
SU
DS39026C-page 257
:
DAT
250 ns must