PIC18C442-I/P Microchip Technology, PIC18C442-I/P Datasheet
PIC18C442-I/P
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PIC18C442-I/P Summary of contents
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... High Performance Microcontrollers 2001 Microchip Technology Inc. PIC18CXX2 Data Sheet with 10-bit A/D DS39026C ...
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... Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights.” ...
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... EPROM # Single Word (bytes) Instructions PIC18C242 16K 8192 PIC18C252 32K 16384 PIC18C442 16K 8192 PIC18C452 32K 16384 • MIPs operation MHz osc./clock input - 4 MHz - 10 MHz osc./clock input with PLL active • 16-bit wide instructions, 8-bit wide data path • Priority levels for interrupts • ...
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... RB3/CCP2 * RB3 is the alternate pin for the CCP2 pin multiplexing. Note: Pin compatible with 44-pin PIC16C7X devices. DS39026C-page PIC18C4X2 PIC18C4X2 RB3/CCP2 RB2/INT2 RB1/INT1 RB0/INT0 RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN RA4/T0CKI 2001 Microchip Technology Inc. ...
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... DIP, SOIC, JW MCLR/V RA0/AN0 RA1/AN1 RA2/AN2/V RA3/AN3/V RA4/T0CKI RA5/AN4/SS/LVDIN OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL * RB3 is the alternate pin for the CCP2 pin multiplexing. Note: Pin compatible with 28-pin PIC16C7X devices. 2001 Microchip Technology Inc. 1 RB7 PP 40 RB6 RB5 RB4 37 + RB3/CCP2 ...
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... Appendix C: Conversion Considerations........................................................................................................................................ 288 Appendix D: Migration from Baseline to Enhanced Devices .......................................................................................................... 288 Appendix E: Migration from Mid-Range to Enhanced Devices ...................................................................................................... 289 Appendix F: Migration from High-End to Enhanced Devices ......................................................................................................... 289 Index ................................................................................................................................................................................................. 291 On-Line Support................................................................................................................................................................................ 299 Reader Response ............................................................................................................................................................................. 300 PIC18CXX2 Product Identification System ....................................................................................................................................... 301 DS39026C-page 4 2001 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2001 Microchip Technology Inc. PIC18CXX2 DS39026C-page 5 ...
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... PIC18CXX2 NOTES: DS39026C-page 6 2001 Microchip Technology Inc. ...
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... Stack Full, Stack Full, Stack Underflow (PWRT, OST) (PWRT, OST) Yes Yes Yes Yes 75 Instructions 75 Instructions 28-pin DIP 28-pin DIP 28-pin SOIC 28-pin SOIC 28-pin JW 28-pin JW PIC18CXX2 PIC18C442 PIC18C452 MHz MHz 16K 32K 8192 16384 512 1536 17 17 Ports Ports MSSP, ...
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... DD SS Timer2 Timer3 Master Addressable Synchronous USART Serial Port PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS/LVDIN RA6 PORTB RB0/INT0 RB1/INT1 RB2/INT2 (1) RB3/CCP2 RB7:RB4 8 8 PORTC RC0/T1OSO/T1CKI (1) RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT A/D Converter 2001 Microchip Technology Inc. ...
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... The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction). 3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent. 2001 Microchip Technology Inc. Data Bus<8> Data Latch ...
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... Digital I/O. Open drain when configured as output Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog input SPI Slave Select input. I Analog Low Voltage Detect Input. See the OSC2/CLKO/RA6 pin. CMOS = CMOS compatible input or output P = Power ) DD Description 2001 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input O = Output OD = Open Drain (no P diode to V 2001 Microchip Technology Inc. Pin Buffer Type PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... I/O ST Digital I/ USART Asynchronous Receive. I/O ST USART Synchronous Data (see related TX/CK). P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output P = Power ) DD Description 2 C mode. 2001 Microchip Technology Inc. ...
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... RA5 AN4 SS LVDIN RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input O = Output OD = Open Drain (no P diode to V 2001 Microchip Technology Inc. Pin Buffer Type Type 18 Master clear (input) or programming voltage (input Master Clear (Reset) input. This pin is an active low RESET to the device ...
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... TTL Digital I/O. Interrupt-on-change pin. 15 I/O TTL Digital I/O. Interrupt-on-change pin. 16 I/O TTL Digital I/O. Interrupt-on-change pin ICSP programming clock. 17 I/O TTL Digital I/O. Interrupt-on-change pin. I/O ST ICSP programming data. CMOS = CMOS compatible input or output P = Power ) DD Description 2001 Microchip Technology Inc. ...
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... TX CK RC7/RX/ RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input O = Output OD = Open Drain (no P diode to V 2001 Microchip Technology Inc. Pin Buffer Type Type PORTC is a bi-directional I/O port. 32 I/O ST Digital I/O. O — Timer1 oscillator output. ...
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... Chip Select control for parallel slave port (see related RD and WR). Analog Analog input 7. P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output P = Power ) DD Description 2001 Microchip Technology Inc. ...
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... C1 and C2 series resistor (R ) may be required for AT S strip cut crystals varies with the osc mode chosen. F 2001 Microchip Technology Inc. TABLE 2-1: Mode XT HS 16.0 MHz These values are for design guidance only. See notes following this table. ...
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... I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). EXTERNAL CLOCK INPUT OPERATION (HS CONFIGURATION) OSC1 PIC18CXXX OSC2 ) and capacitor (C ) val- EXT EXT values. The user also needs to take RC OSCILLATOR MODE Internal OSC1 Clock PIC18CXXX OSC2/CLKO /4 R 100 k EXT C > 20pF EXT 2001 Microchip Technology Inc. ...
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... OSC2 Comparator F IN Crystal Osc F OSC1 2001 Microchip Technology Inc. FIGURE 2-5: Clock from Ext. System 2.5 HS/PLL A Phase Locked Loop circuit is provided as a program- mable option for users that want to multiply the fre- quency of the incoming crystal oscillator signal by 4. ...
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... U-0 U-0 U-0 U-0 — — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared /4 T SCLK Clock Source U-0 U-0 R/W-1 — — — SCS bit Bit is unknown 2001 Microchip Technology Inc. ...
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... OST OSC 2001 Microchip Technology Inc. A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-8. The Timer1 oscillator is assumed to be run- ning all the time. After the SCS bit is set, the processor is frozen at the next occurring Q1 cycle ...
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... A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS-PLL mode, is shown in Figure 2-10 PLL T SCS T OSC cating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes, is shown in Figure 2-11 OSC SCS 2001 Microchip Technology Inc. ...
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... BOR). The second timer is the Oscillator Start-up Timer, OST, intended to keep the chip in RESET until the crystal oscillator is stable. 2001 Microchip Technology Inc. switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents) ...
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... PIC18CXX2 NOTES: DS39026C-page 24 2001 Microchip Technology Inc. ...
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... RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: See Table 3-1 for time-out situations. 2001 Microchip Technology Inc. PIC18CXX2 Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different RESET situations, as indicated in Table 3-2 ...
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... PIC18CXXX device oper- ating in parallel. Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all the registers. 2001 Microchip Technology Inc. falls below DD rises above DD while the ...
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... Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit, read as '0'. Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2001 Microchip Technology Inc. (2) Power-up Brown-out PWRTE = 1 ...
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... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu -u-u (1) uu-u u-uu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A 2001 Microchip Technology Inc. ...
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... The long write enable is only reset on a POR or MCLR Reset. 7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’. 2001 Microchip Technology Inc. MCLR Resets Power-on Reset, ...
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... Microchip Technology Inc. ...
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... The long write enable is only reset on a POR or MCLR Reset. 7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’. 2001 Microchip Technology Inc. MCLR Resets Power-on Reset, ...
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... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39026C-page 32 T PWRT T OST T PWRT T OST T PWRT T OST 2001 Microchip Technology Inc CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL 2001 Microchip Technology Inc PWRT T OST T PWRT T OST T PLL PIC18CXX2 ...
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... PIC18CXX2 NOTES: DS39026C-page 34 2001 Microchip Technology Inc. ...
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... NOP instruction). PIC18C252 and PIC18C452 have 32 Kbytes of EPROM, while PIC18C242 and PIC18C442 have 16 Kbytes of EPROM. This means that PIC18CX52 devices can store up to 16K of single word instructions, and PIC18CX42 devices can store single word instructions ...
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... PIC18CXX2 FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR PIC18C442/242 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 31 RESET Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-chip Program Memory 3FFFh 4000h Read ’0’ 1FFFFFh 200000h DS39026C-page 36 ...
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... At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user must disable the global interrupt enable bits during this time to prevent inadvertent stack opera- tions.. 2001 Microchip Technology Inc. PIC18CXX2 4.2.2 RETURN STACK POINTER (STKPTR) ...
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... RESET. When the STVREN bit is enabled, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device RESET. The STKFUL or STKUNF bits are only cleared by the user software or a POR Reset. R/W-0 R/W-0 SP1 SP0 bit Bit is unknown 00010 2001 Microchip Technology Inc. ...
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... PC PC OSC2/CLKOUT (RC mode) Execute INST (PC-2) Fetch INST (PC) 2001 Microchip Technology Inc. 4.4 PCL, PCLATH and PCLATU The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte is called the PCL register. This reg- ister is readable and writable. The high byte is called the PCH register. This register contains the PC< ...
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... LSB = 1 LSB = 0 0Fh 55h 055h EFh 03h 000006h F0h 00h C1h 23h 123h, 456h F4h 56h Flush (NOP) Fetch SUB_1 Execute SUB_1 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2001 Microchip Technology Inc. ...
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... In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. 2001 Microchip Technology Inc. second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that changes the PC ...
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... The SFRs are typically distributed among the peripher- als whose functions they control. The unused SFR locations will be unimplemented and read as '0's. See Table 4-1 for addresses for the SFRs. 2001 Microchip Technology Inc. ...
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... Bank 1110b Bank 14 00h = 1111b Bank 15 FFh When the BSR is used to specify the RAM location that the instruc- tion uses. 2001 Microchip Technology Inc. Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh 200h Unused Read ’00h’ ...
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... Access RAM high FFh (SFR’s) When the BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). 2001 Microchip Technology Inc. ...
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... PLUSW1 FC3h FE2h FSR1H FC2h FE1h FSR1L FC1h FE0h BSR FC0h Note 1: Unimplemented registers are read as ’0’. 2: This register is not available on PIC18C2X2 devices. 3: This is not a physical register. 2001 Microchip Technology Inc. (3) INDF2 FBFh CCPR1H (3) POSTINC2 FBEh CCPR1L (3) POSTDEC2 FBDh CCP1CON (3) ...
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... N/A 50 N/A 50 N/A 50 N ---- 0000 50 xxxx xxxx 49 ---- 0000 N/A 50 N/A 50 N/A 50 N ---- 0000 50 xxxx xxxx ---x xxxx 95 0000 0000 95 xxxx xxxx T0PS1 T0PS0 93 1111 1111 — SCS 20 ---- ---0 LVDL1 LVDL0 175 --00 0101 2001 Microchip Technology Inc. ...
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... Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 2001 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 — ...
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... TMR1IP 72 1111 1111 TMR1IF 68 0000 0000 TMR1IE 70 0000 0000 88 0000 -111 85 1111 1111 83 1111 1111 80 1111 1111 77 -111 1111 87 ---- -xxx 85 xxxx xxxx 83 xxxx xxxx 80 xxxx xxxx 77 -xxx xxxx 87 ---- -000 85 xxxx xxxx 83 xxxx xxxx 80 xxxx xxxx 77 -x0x 0000 2001 Microchip Technology Inc. ...
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... The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the reg- isters of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. 2001 Microchip Technology Inc. can be accessed without any software overhead. This is useful for testing status flags and modifying control bits ...
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... FSR to form the address before an indirect access. The FSR value is not changed FSR register contains a value that points to one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (STATUS bits are not affected). 2001 Microchip Technology Inc. ...
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... INDIRECT ADDRESSING OPERATION Instruction Executed Instruction Fetched FIGURE 4-10: INDIRECT ADDRESSING Indirect Addressing 11 FSR Register Location Select Note 1: For register file map detail, see Table 4-1. 2001 Microchip Technology Inc. Opcode Address 12 File Address = access of an indirect addressing register BSR<3:0> Opcode File ...
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... The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown 2001 Microchip Technology Inc. ...
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... A Brown-out Reset has not occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. PIC18CXX2 . Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is ’1’ Power-on Reset. After a Brown- ...
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... PIC18CXX2 NOTES: DS39026C-page 54 2001 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2001 Microchip Technology Inc. PIC18CXX2 Table Read operations retrieve data from program memory and place it into the data memory space. Figure 5-1 shows the operation of a Table Read with program and data memory ...
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... The LWRT bit can be cleared only by performing either a POR or MCLR Reset. U-0 R/W-1 R/W-1 R/W-1 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared voltage is applied to the PP R/W-0 R/W-0 POR BOR bit Bit is unknown 2001 Microchip Technology Inc. ...
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... For PIC18CXX2 devices, the write block size is 2 bytes. Consequently, Table Write opera- tions to internal program memory are performed in pairs, one byte at a time. 2001 Microchip Technology Inc. 5.1.3 TBLPTR - TABLE POINTER REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory ...
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... SLEEP mode, as the clocks and peripherals will continue to run.) The interrupt will cause the microcontroller to resume operation. 10. If GIE was set, service the interrupt request. 11. Lower MCLR/V pin 12. Verify the memory location (Table Read). 2001 Microchip Technology Inc. global ...
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... Microchip Technology Inc. Depending on the states of interrupt priority bits, the GIE/GIEH bit or the PIE/GIEL bit, program execution can either be vectored to the high or low priority Inter- rupt Service Routine (ISR), or continue execution from where programming commenced ...
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... PIC18CXX2 NOTES: DS39026C-page 60 2001 Microchip Technology Inc. ...
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... ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL 2001 Microchip Technology Inc. PIC18CXX2 Making the multiplier execute in a single cycle gives the following advantages: • Higher computational throughput • Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors ...
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... MOVF ARG2L, W SUBWF RES2 MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE : SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ARG1H * ARG2H -> ; PRODH:PRODL ; ARG1L * ARG2H -> ; PRODH:PRODL ; F ; Add cross ; products ARG1H * ARG2L -> ; PRODH:PRODL ; F ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; 2001 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. 2001 Microchip Technology Inc. PIC18CXX2 When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- ® ...
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... INT1IP INT2IF INT2IE INT2IP IPE IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP 2001 Microchip Technology Inc. Wake- SLEEP mode Interrupt to CPU Vector to location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEL\PEIE ...
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... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2001 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ...
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... This feature allows for software polling. DS39026C-page 66 R/W-1 R/W-1 U-0 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 U-0 R/W-1 — RBIP bit Bit is unknown 2001 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2001 Microchip Technology Inc. PIC18CXX2 U-0 R/W-0 ...
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... R-0 R-0 R/W-0 ADIF RCIF TXIF SSPIF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCP1IF TMR2IF TMR1IF bit Bit is unknown 2001 Microchip Technology Inc. ...
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... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 — — — BCLIF W = Writable bit U = Unimplemented bit, read as ‘ ...
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... Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR DS39026C-page 70 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown 2001 Microchip Technology Inc. ...
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... Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 — — — BCLIE W = Writable bit U = Unimplemented bit, read as ‘ ...
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... Low priority Legend Readable bit - n = Value at POR DS39026C-page 72 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2001 Microchip Technology Inc. ...
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... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. U-0 U-0 U-0 R/W-1 — — — BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... For details of bit operation, see Register 4-3 Legend Readable bit - n = Value at POR reset DS39026C-page 74 U-0 R/W-1 R-1 R-1 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared 2001 Microchip Technology Inc. R/W-0 R/W-0 POR BOR bit Bit is unknown ...
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... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2001 Microchip Technology Inc. 7.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (FFFFh TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON< ...
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... PIC18CXX2 NOTES: DS39026C-page 76 2001 Microchip Technology Inc. ...
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... The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. 2001 Microchip Technology Inc. EXAMPLE 8-1: CLRF PORTA CLRF LATA ...
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... I/O pin N WR LATA or CK PORTA V Data Latch TRISA TRIS Latch Data Bus RD TRISA Data Bus and PORTA Note 1: I/O pins have protection diodes to V BLOCK DIAGRAM OF RA6 RD LATA (1) I/O pin ECRA6 or RCRA6 Enable TTL Input Buffer and 2001 Microchip Technology Inc. ...
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... PORTA Data Direction Register ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by PORTA. 2001 Microchip Technology Inc. Input/output or analog input. Input/output or analog input. Input/output or analog input or V Input/output or analog input Input/output or external clock input for Timer0. ...
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... D RD PORTB EN Set RBIF Q D From other EN RB7:RB4 pins RBx/INTx Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2001 Microchip Technology Inc Weak P Pull-up I/O (1) pin ST Buffer Q1 RD PORTB Q3 and V ...
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... Buffer Note 1: I/O pin has diode protection enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>). 3: The CCP2 input/output is multiplexed with RB3, if the CCP2MX bit is enabled (=’0’) in the configuration register. 2001 Microchip Technology Inc Weak ...
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... INT2IE INT1IE — INT2IF Value on Value on all Bit 0 POR, other BOR RESETS RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 000x 0000 000u RBIP 1111 -1-1 1111 -1-1 INT1IF 11-0 0-00 11-0 0-00 2001 Microchip Technology Inc. ...
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... Note 1: I/O pins have diode protection Port/Peripheral select signal selects between port data (input) and peripheral output. 3: Peripheral Output Enable is only active if peripheral select is active. 2001 Microchip Technology Inc. The pin override value is not loaded into the TRIS reg- ister. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides ...
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... Input/output port pin, Addressable USART Asynchronous Receive, or Addressable USART Synchronous Data. Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 RC2 RC1 2 C mode). Value on Value on all Bit 0 POR, other BOR RESETS RC0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 2001 Microchip Technology Inc. ...
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... LATD ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2001 Microchip Technology Inc. PIC18CXX2 FIGURE 8-8: PORTD BLOCK DIAGRAM IN I/O PORT MODE RD LATD Data Bus LATD CK or ...
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... Bit 2 Bit 1 RD4 RD3 RD2 RD1 — PORTE Data Direction bits Function Value on Value on all Bit 0 POR, other BOR RESETS RD0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 2001 Microchip Technology Inc. ...
Page 89
... Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 0x03 ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs 2001 Microchip Technology Inc. PIC18CXX2 FIGURE 8-9: PORTE BLOCK DIAGRAM IN I/O PORT MODE RD LATE Data Bus LATE CK or PORTE ...
Page 90
... Legend Readable bit - n = Value at POR DS39026C-page 88 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 R/W-1 TRISE2 TRISE1 TRISE0 bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 91
... IBOV PSPMODE ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PORTE. 2001 Microchip Technology Inc. Function Input/output port pin or read control input in Parallel Slave Port mode or analog input: ( Not a read operation 0 = Read operation. Reads PORTD register (if chip selected). ...
Page 92
... Data Latch Q RD PORTD RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pin has protection diodes PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Q RDx pin TTL Read RD TTL Chip Select CS TTL Write WR TTL and 2001 Microchip Technology Inc. ...
Page 93
... RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. 2001 Microchip Technology Inc Bit 4 Bit 3 Bit 2 Bit 1 — — RE2 RE1 — ...
Page 94
... PIC18CXX2 NOTES: DS39026C-page 92 2001 Microchip Technology Inc. ...
Page 95
... Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. PIC18CXX2 Figure 9-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 9-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
Page 96
... PSA T0PS2, T0PS1, T0PS0 0 Sync with Internal TMR0L Clocks delay) CY PSA Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2001 Microchip Technology Inc. ...
Page 97
... PORTA Data Direction Register Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 2001 Microchip Technology Inc. 9.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “on-the-fly” during program execution) ...
Page 98
... PIC18CXX2 NOTES: DS39206C-page 96 2001 Microchip Technology Inc. ...
Page 99
... Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. Figure 10 simplified block diagram of the Timer1 module. Register 10-1 details the Timer1 control register. This register controls the operating mode of the Timer1 module, and contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled or disabled by set- ting or clearing control bit TMR1ON (T1CON< ...
Page 100
... Clock T1CKPS1:T1CKPS0 TMR1CS 8 CCP Special Event Trigger CLR TMR1L TMR1ON On/Off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized Clock Input Synchronize det 2 SLEEP Input Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 SLEEP Input 2001 Microchip Technology Inc. ...
Page 101
... TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clear- ing TMR1 interrupt enable bit TMR1IE (PIE1<0>). 2001 Microchip Technology Inc. 10.4 Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in compare mode to generate a “ ...
Page 102
... Bit 0 all other POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON --00 0000 --uu uuuu 2001 Microchip Technology Inc. ...
Page 103
... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. 11.1 Timer2 Operation Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (F of 1:1, 1:4, or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON< ...
Page 104
... TMR2IF Value on Value on Bit 0 all other POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 2001 Microchip Technology Inc. ...
Page 105
... Enables Timer3 0 = Stops Timer3 Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. Figure 12 simplified block diagram of the Timer3 module. Register 12-1 shows the Timer3 control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 106
... Internal 0 (1) Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Trigger T3CCPx TMR3 CLR TMR3L TMR3ON On/Off OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Synchronized Clock Input Synchronize det 2 SLEEP Input Synchronized 0 Clock Input 1 T3SYNC Synchronize Prescaler det 2 SLEEP Input 2001 Microchip Technology Inc. ...
Page 107
... RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. 2001 Microchip Technology Inc. 12.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3 ...
Page 108
... PIC18CXX2 NOTES: DS39206C-page 106 2001 Microchip Technology Inc. ...
Page 109
... Trigger special event (CCPIF bit is set) 11xx = PWM mode Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger. Therefore, operation of a CCP module in the following sections is described with respect to CCP1. ...
Page 110
... None. PWM Compare None. DS39026C-page 108 13.2 CCP2 Module Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. Interaction 2001 Microchip Technology Inc. ...
Page 111
... CCP2 pin and Edge Detect CCP2CON<3:0> Q’s 2001 Microchip Technology Inc. 13.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode ...
Page 112
... Set Flag bit CCP1IF Output Logic Match CCP1CON<3:0> T3CCP2 Mode Select TMR1H Set Flag bit CCP2IF T3CCP1 T3CCP2 Output Logic Match CCP2CON<3:0> Mode Select CCPR1H CCPR1L Comparator 1 0 TMR1L TMR3H TMR3L 0 1 Comparator CCPR2H CCPR2L 2001 Microchip Technology Inc. ...
Page 113
... T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear. 2001 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 ...
Page 114
... PWM Resolution (max) Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. • OSC (TMR2 prescale value) T • (TMR2 prescale value) OSC F OSC --------------- log F PWM = -----------------------------bits log 2 2001 Microchip Technology Inc. ...
Page 115
... Shaded cells are not used by PWM and Timer2. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear. 2001 Microchip Technology Inc. 3. Make the CCP1 pin an output by clearing the TRISC< ...
Page 116
... PIC18CXX2 NOTES: DS39026C-page 114 2001 Microchip Technology Inc. ...
Page 117
... Serial Peripheral Interface (SPI ) 2 • Inter-Integrated Circuit ( Full Master mode - Slave mode (with general address call) 2 The I C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode 2001 Microchip Technology Inc. PIC18CXX2 DS39026C-page 115 ...
Page 118
... STOP bit was not detected last Legend Readable bit - n = Value at POR DS39026C-page 116 R-0 R-0 R-0 D mode only Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 119
... C mode only Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. R-0 R-0 R-0 CKE D/A ...
Page 120
... DS39026C-page 118 R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 2 C conditions were not valid for Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 121
... I C Slave mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 ...
Page 122
... C Master mode only Master mode only Master mode only module is not in the Idle mode Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 RSEN SEN bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 123
... Clock edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) Figure 14-1 shows the block diagram of the MSSP module, when in SPI mode. 2001 Microchip Technology Inc. PIC18CXX2 FIGURE 14-1: MSSP BLOCK DIAGRAM (SPI MODE) Read ...
Page 124
... SCK (Master mode) must have TRISC<3> bit cleared • SCK (Slave mode) must have TRISC<3> bit set • SS must have TRISC<4> bit set Any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (TRIS) register to the opposite value. 2001 Microchip Technology Inc. ...
Page 125
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2001 Microchip Technology Inc. trollers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: • Master sends data — Slave sends dummy data • ...
Page 126
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit5 bit4 bit2 bit1 bit3 bit5 bit4 bit2 bit1 bit3 ) ) 4 Clock modes bit0 bit0 bit0 bit0 Next Q4 cycle after Q2 2001 Microchip Technology Inc. ...
Page 127
... SSPIF Interrupt Flag SSPSR to SSPBUF 2001 Microchip Technology Inc. the SDO pin is no longer driven, even if in the mid- dle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON< ...
Page 128
... SDO bit7 SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39026C-page 126 bit6 bit5 bit4 bit2 bit3 bit6 bit2 bit5 bit4 bit3 bit1 bit0 bit0 Next Q4 cycle after Q2 bit1 bit0 bit0 Next Q4 cycle after Q2 2001 Microchip Technology Inc. ...
Page 129
... D/A Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear. 2001 Microchip Technology Inc. 14.3.9 BUS MODE COMPATIBILITY ...
Page 130
... The SCL clock input must have a minimum high and low for proper operation. The high and low times of the specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 and parameter #101 oper modes to be selected mode with the SSPEN bit set, 2001 Microchip Technology Inc. ...
Page 131
... Receive first (high) byte of Address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 2001 Microchip Technology Inc. PIC18CXX2 14.4.1.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared ...
Page 132
... SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Receiving Data Not ACK Bus Master terminates transfer ACK is not sent. R Transmitting Data Not ACK From SSP Interrupt Service Routine 2001 Microchip Technology Inc. ...
Page 133
... I FIGURE 14-10: C SLAVE MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) 2001 Microchip Technology Inc. PIC18CXX2 DS39026C-page 131 ...
Page 134
... PIC18CXX2 2 FIGURE 14-11 SLAVE MODE WAVEFORM (RECEPTION 10-BIT ADDRESS) DS39026C-page 132 2001 Microchip Technology Inc. ...
Page 135
... In Master mode, the SCL and SDA lines are manipu- lated by the MSSP hardware. 2001 Microchip Technology Inc. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set ...
Page 136
... START bit, STOP bit, Acknowledge Generate START bit Detect STOP bit Detect Write Collision Detect Set/Reset WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV 2 C SSPM3:SSPM0 SSPADD<6:0> Baud Rate Generator 2001 Microchip Technology Inc. ...
Page 137
... SSPBUF. Once the given operation is complete, (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. 2001 Microchip Technology Inc. PIC18CXX2 A typical transmit sequence would go as follows: a) ...
Page 138
... BRG Down Counter CLKOUT DX-1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count the Master mode, the BRG OSC 03h 02h 2001 Microchip Technology Inc. ...
Page 139
... FIGURE 14-16: FIRST START BIT TIMING Write to SEN bit occurs here. SDA SCL 2001 Microchip Technology Inc. 14.4.6.1 WCOL Status Flag If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the con- tents of the buffer are unchanged (the write doesn’t occur) ...
Page 140
... SSPCON2 is disabled until the Repeated START condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 hardware clear RSEN bit and set SSPIF BRG BRG BRG Write to SSPBUF occurs here Repeated START 1st Bit T BRG BRG 2001 Microchip Technology Inc. ...
Page 141
... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 2001 Microchip Technology Inc. PIC18CXX2 14.4.8.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
Page 142
... PIC18CXX2 2 FIGURE 14-18 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39026C-page 140 2001 Microchip Technology Inc. ...
Page 143
... FIGURE 14-19 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2001 Microchip Technology Inc. PIC18CXX2 DS39026C-page 141 ...
Page 144
... WCOL bit is set and the con- tents of the buffer are unchanged (the write doesn’t occur). ACKEN automatically cleared T T BRG BRG D0 ACK 8 9 Cleared in software Set SSPIF at the end of Acknowledge sequence (baud rate BRG BRG Cleared in software 2001 Microchip Technology Inc. ...
Page 145
... Release SCL, Slave device holds SCL low. SCL SDA T BRG 2001 Microchip Technology Inc. SCL = 1 for Tbrg, followed by SDA = 1 for Tbrg after SDA sampled high. P bit (SSPSTAT<4>) is set PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T ...
Page 146
... S and P bits are cleared. Sample SDA. While SCL is high SDA line pulled low by another source data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by master 2 C Set bus collision interrupt (BCLIF) 2001 Microchip Technology Inc. ...
Page 147
... BCLIF SDA = 0, SCL = 1. S SSPIF 2001 Microchip Technology Inc. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 14-26). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count ...
Page 148
... Bus collision occurs, set BCLIF SDA = 0, SCL = 1 Set S Set SSPIF BRG T BRG S SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 SDA = 0, SCL = 1 Set SSPIF Interrupt cleared in software ’0’ ’0’ ’0’ Interrupts cleared in software 2001 Microchip Technology Inc. ...
Page 149
... BCLIF Set BCLIF. Release SDA and SCL. RSEN S SSPIF 2001 Microchip Technology Inc. reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs ...
Page 150
... This is another case of another master attempt- ing to drive a data ’0’ (Figure 14-30 BRG BRG T BRG SCL goes low before SDA goes high Set BCLIF SDA sampled T BRG low after T , BRG Set BCLIF ’0’ ’0’ T BRG ’0’ ’0’ 2001 Microchip Technology Inc. ...
Page 151
... TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit. Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) ...
Page 152
... Value at POR reset DS39026C-page 150 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 153
... SPEN RX9 SREN SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used by the BRG. 2001 Microchip Technology Inc. Example 15-1 shows the calculation of the baud rate error for the following conditions: • MHz OSC • Desired Baud Rate = 9600 • ...
Page 154
... SPBRG Actual SPBRG % value Rate value Error (decimal) (K) (decimal) —— NA — — — NA — — — NA — — 103 9.622 +0. 19.04 -0. 74.57 -2. 99.43 +3.57 8 — 298.3 -0.57 2 — NA — — 0 894.9 — 0 255 3.496 — 255 2001 Microchip Technology Inc. ...
Page 155
... NA — — — — 300 NA — — 500 NA — — HIGH 15.63 — 0 0.512 LOW 0.0610 — 255 0.0020 2001 Microchip Technology Inc MHz MHz OSC OSC SPBRG Actual % % value Rate Error Error (K) (decimal) (K) NA — — NA — +1.73 255 1.202 +0 ...
Page 156
... NA — — 3.579545 MHz OSC SPBRG Actual SPBRG % value Rate value Error (decimal) (K) (decimal) — 9.727 +1.32 22 207 18.643 -2.90 11 103 37.286 -2. 55.930 -2. 111.86 -2.90 1 — 223.72 -10.51 0 — NA — — — NA — — 2001 Microchip Technology Inc. ...
Page 157
... Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator 2001 Microchip Technology Inc. data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one T flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXIE ( PIE1< ...
Page 158
... START Bit Bit 0 STOP Bit Word 2 Value on Value on Bit 0 POR, all other BOR RESETS RBIF 0000 000x 0000 000u RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...
Page 159
... USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK SPBRG Baud Rate Generator RC7/RX/DT Pin Buffer and Control SPEN 2001 Microchip Technology Inc. 15.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. ...
Page 160
... STOP bit7/8 bit bit Value on Value on POR, all other BOR RESETS 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...
Page 161
... Shaded cells are not used for Synchronous Master Transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear. 2001 Microchip Technology Inc. rupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1< ...
Page 162
... Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words. FIGURE 15-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit DS39026C-page 160 Bit 1 Bit 2 Bit 7 Bit 0 Word 1 bit0 bit2 bit1 Bit 1 Bit 7 Word 2 ’1’ bit6 bit7 2001 Microchip Technology Inc. ...
Page 163
... RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRGH = ’0’. 2001 Microchip Technology Inc. 3. Ensure bits CREN and SREN are clear interrupts are desired, set enable bit RCIE 9-bit reception is desired, set bit RX9. ...
Page 164
... FERR OERR SYNC — BRGH TRMT Value on Value on all Bit 0 POR, other BOR RESETS RBIF 0000 000x 0000 000u RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...
Page 165
... Shaded cells are not used for Synchronous Slave Reception. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear. 2001 Microchip Technology Inc. To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC ...
Page 166
... PIC18CXX2 NOTES: DS39026C-page 164 2001 Microchip Technology Inc. ...
Page 167
... A/D converter module is powered A/D converter module is shut-off and consumes no operating current Legend Readable bit - n = Value at POR reset 2000 Microchip Technology Inc. The A/D module has four registers. These registers are: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • ...
Page 168
... Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit 0 AN1 AN0 REF REF AN3 AN3 AN3 — — AN3 AN2 AN3 AN3 AN2 AN3 AN2 AN3 AN2 AN3 AN2 Bit is unknown 2000 Microchip Technology Inc. ...
Page 169
... REF Reference voltage V REF 2000 Microchip Technology Inc. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a volt- age reference digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ ADRESL registers, the GO/DONE bit (ADCON0< ...
Page 170
... Note: When the conversion is started, the hold- ing capacitor is disconnected from the input pin Sampling Switch leakage V = 0.6V T ± 500 must be allowed HOLD ) and the internal sampling S . The sampling HOLD 120 pF HOLD Sampling Switch (k ) 2000 Microchip Technology Inc. ...
Page 171
... CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME ACQ AMP C COFF Temperature coefficient is only required for temperatures > [(Temp - 25 C)(0.05 s/ C)] ACQ ln(1/2047) C HOLD -120 2 ln(0.0004885) -120 pF (10 ln(0.0004885) -1.26 s (-7.6241 C)(0.05 s/ C)] ACQ 11. 1.25 s 12.86 s 2000 Microchip Technology Inc. time, (-Tc HOLD ln(1/2047) PIC18CXX2 DS39026C-page 169 ...
Page 172
... AD time will be converted 1.25 MHz 333.33 kHz 1 3 (3) 6 (3) 12 (3) (3) 25 (3) (3) 51.2 s 192 s (1) ( 1.25 MHz 333.33 kHz (2) 1 (2) 3 (3) 6 (3) 12 (3) (3) 25 (3) (3) 51.2 s 192 s (1,4) (1, 2000 Microchip Technology Inc. ...
Page 173
... Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2000 Microchip Technology Inc. 16.5 Use of the CCP2 Trigger An A/D conversion can be started by the “special event trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- grammed as 1011 and that the A/D module is enabled (ADON bit is set) ...
Page 174
... CCP2IP ---- 0000 ---- 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ADON 0000 00-0 0000 00-0 PCFG0 ---- -000 ---- -000 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 RE0 ---- -000 ---- -000 LATE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 2000 Microchip Technology Inc. ...
Page 175
... The “trip point” voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the 2000 Microchip Technology Inc. The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be “turned off” ...
Page 176
... LVD Control Register Internally Generated Nominal Reference Voltage 1.2V This gives flexibility, because it allows a user to config- ure the Low Voltage Detect interrupt to occur at any voltage in the valid operating range VxEN BODEN EN LVDIF LVD Control Register LVDEN LVD BGAP 2000 Microchip Technology Inc. ...
Page 177
... Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. Legend Readable bit U = Unimplemented bit, read as ‘0’ 2000 Microchip Technology Inc. U-0 R-0 R/W-0 R/W-0 — IRVST ...
Page 178
... Figure 17-4 shows typical waveforms that the LVD module may be used to detect. LVDIF may not be set 50 ms LVDIF cleared in software 50 ms LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists 2000 Microchip Technology Inc. V LVD V LVD ...
Page 179
... The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. 2000 Microchip Technology Inc. PIC18CXX2 17.3 Operation During SLEEP When enabled, the LVD circuitry continues to operate during SLEEP ...
Page 180
... PIC18CXX2 NOTES: DS39026C-page 178 2000 Microchip Technology Inc. ...
Page 181
... DEV10 DEV9 Legend unknown unchanged unimplemented value depends on condition. Shaded cells are unimplemented, read as ‘0’ 2000 Microchip Technology Inc. SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application ...
Page 182
... U = Unimplemented bit, read as ‘0’ Unchanged from programmed state R/P-1 R/P-1 R/P Programmable bit U = Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 R/P-1 R/P-1 R/P-1 — FOSC2 FOSC1 FOSC0 bit 0 ) OSC R/P-1 R/P-1 R/P bit 0 2000 Microchip Technology Inc. ...
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... Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. Legend Readable bit - n = Value when device is unprogrammed 2000 Microchip Technology Inc. U-0 U-0 R/P-1 — — — ...
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... Unchanged from programmed state U-0 U-0 U-0 U-0 — — — — Programmable bit U = Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 U-0 R/P-1 — — CCP2MX bit 0 U-0 R/P-1 R/P-1 — Reserved STVREN bit 0 2000 Microchip Technology Inc. ...
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... Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = ’0’ Legend Readable bit U = Unimplemented bit, read as ‘0’ 2000 Microchip Technology Inc. The WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT postscaler may be assigned using the configuration bits. ...
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... Legend: Shaded cells are not used by the Watchdog Timer. DS39026C-page 184 Postscaler MUX WDT Time-out Bit 5 Bit 4 Bit 3 — — WDTPS2 WDTPS2 — — — — WDTPS2:WDTPS0 Bit 2 Bit 1 Bit 0 WDTPS0 WDTEN PD POR BOR — — SWDTEN 2000 Microchip Technology Inc. ...
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... RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared WDT time-out occurred (and caused wake-up). 2000 Microchip Technology Inc. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
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... Protection If the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. Note: Microchip Technology does not recom- mend code protecting windowed devices. 18.5 ID Locations Five memory locations (200000h - 200004h) are desig- nated as ID locations, where the user can store check- sum or other code identification numbers ...
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... The desired FSR register to load the literal value into (specified by ‘f’) • No operand required (specified by ‘—’) 2001 Microchip Technology Inc. PIC18CXX2 The control instructions may use some of the following operands: • A program memory address (specified by ‘n’) • ...
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... GIE Watchdog Timer WDT Time-out bit TO Power-down bit PD ALU status bits Carry, Digit Carry, Zero, Overflow, Negative C, DC, Z, OV, N Optional [ ] Contents ( ) Assigned to Register bit field < > In the set of User defined term (font is courier) italics DS39026C-page 188 Description 2001 Microchip Technology Inc. ...
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... Control operations CALL, GOTO and Branch operations 15 OPCODE 1111 n = 20-bit immediate value 15 OPCODE Fast bit OPCODE 15 OPCODE 2001 Microchip Technology Inc. Example Instruction (FILE #) ADDWF MYREG (Source FILE #) MOVFF MYREG1, MYREG2 0 f (Destination FILE #) BSF MYREG, bit (FILE #) 8 7 ...
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... Microchip Technology Inc. Status Notes Affected C, DC DC None 4 None 4 None DC None None DC ...
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... This ensures that all program memory locations have a valid instruction the table write starts the write cycle to internal memory, the write will continue until terminated. 2001 Microchip Technology Inc. PIC18CXX2 16-bit Instruction Word ...
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... Microchip Technology Inc. Status Notes Affected C, DC None None None None None C, DC None None None None None None ...
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... Q Cycle Activity Decode Read Process literal ’k’ Data Example: ADDLW 0x15 Before Instruction WREG = 0x10 After Instruction WREG = 0x25 2001 Microchip Technology Inc. ADDWF k Syntax: Operands: Operation: kkkk kkkk Status Affected: Encoding: Description: Q4 Write to Words: WREG Cycles: Q Cycle Activity: ...
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... AND literal with WREG [ label ] ANDLW 255 (WREG) .AND. k WREG N,Z 0000 1011 kkkk kkkk The contents of WREG are ANDed with the 8-bit literal 'k'. The result is placed in WREG Read literal Process Write to ’k’ Data WREG ANDLW 0x5F = 0xA3 = 0x03 2001 Microchip Technology Inc. ...
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... Data Example: ANDWF REG Before Instruction WREG = 0x17 REG = 0xC2 After Instruction WREG = 0x02 REG = 0xC2 2001 Microchip Technology Inc [,d [,a] Syntax: Operands: Operation: dest Status Affected: Encoding: ffff ffff Description: Words: Cycles: Q Cycle Activity: If Jump Write to Decode ...
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... PC+2+2n. This instruction is then a two-cycle instruction Read literal Process Write to PC ’n’ Data operation operation operation Read literal Process No ’n’ Data operation HERE BN Jump = address (HERE address (Jump address (HERE+2) 2001 Microchip Technology Inc. ...
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... Data Example: HERE BNC Jump Before Instruction PC = address (HERE) After Instruction If Carry = address (Jump) If Carry address (HERE+2) 2001 Microchip Technology Inc. BNN Syntax: Operands: Operation: Status Affected: Encoding: nnnn nnnn Description: Words: Cycles: Q Cycle Activity: If Jump Write to PC Decode No No operation ...
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... PC+2+2n. This instruction is then a two-cycle instruction Read literal Process Write to PC ’n’ Data operation operation operation Read literal Process No ’n’ Data operation HERE BNZ Jump = address (HERE address (Jump address (HERE+2) 2001 Microchip Technology Inc. ...