ATMEGA165P-16MU Atmel, ATMEGA165P-16MU Datasheet - Page 161

• Manufacturer Part Number: ATMEGA165P-16MU
• Description: IC AVR MCU 16K 16MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165P-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.1
8019K–AVR–11/10
Internal Clock Generation – The Baud Rate Generator
Figure 18-2. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCK bits.
Table 18-1 on page 162
for calculating the UBRR value for each mode of operation using an internally generated clock
source.
DDR_XCK
osc
XCK
Pin
), is loaded with the UBRR value each time the counter has counted down to zero or when
txclk
rxclk
xcki
xcko
fosc
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
contains equations for calculating the baud rate (in bits per second) and
UBRR+1
fosc
Detector
UCPOL
Edge
/2
Figure
osc
/(UBRR+1)). The Transmitter divides the
/4
18-2.
/2
ATmega165P
DDR_XCK
U2X
0
1
0
1
0
1
1
0
UMSEL
161
txclk
rxclk