ATMEGA165P-16MU Atmel, ATMEGA165P-16MU Datasheet - Page 138

• Manufacturer Part Number: ATMEGA165P-16MU
• Description: IC AVR MCU 16K 16MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165P-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.8
8019K–AVR–11/10
Timer/Counter Timing Diagrams
pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register
at the compare match between OCR2A and TCNT2 when the counter increments, and setting
(or clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the coun-
ter decrements. The PWM frequency for the output when using phase correct PWM can be
calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR2A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set.
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 16-8. Timer/Counter Timing Diagram, no Prescaling
Figure 16-9 on page 139
is MAX the OCn pin value is the same as the result of a down-counting compare match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an
up-counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the way
up.
Figure 16-8
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
contains timing data for basic Timer/Counter operation. The figure shows the
MAX - 1
shows the same timing data, but with the prescaler enabled.
Figure 16-7 on page 137
f
OCnxPCPWM
MAX
Figure 16-7 on page
=
----------------- -
N 510
f
clk_I/O
⋅
OCn has a transition from high to low
BOTTOM
137. When the OCR2A value
ATmega165P
I/O
should be replaced by
BOTTOM + 1
138
T2
)