ATMEGA165P-16MU Atmel, ATMEGA165P-16MU Datasheet - Page 134

• Manufacturer Part Number: ATMEGA165P-16MU
• Description: IC AVR MCU 16K 16MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165P-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.6.1
16.7
16.7.1
16.7.2
8019K–AVR–11/10
Modes of Operation
Compare Output Mode and Waveform Generation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The Waveform Generator uses the COM2A[1:0] bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM2A[1:0] = 0 tells the Waveform Generator that no action
on the OC2A Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 16-4 on page
A change of the COM2A[1:0] bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC2A strobe bits.
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM2[1:0]) and Compare
Output mode (COM2A[1:0]) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM2A[1:0] bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-
PWM modes the COM2A[1:0] bits control whether the output should be set, cleared, or toggled
at a compare match.
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGM2[1:0] = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM2[1:0] = 2), the OCR2A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
(TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then coun-
ter (TCNT2) is cleared.
144, and for phase correct PWM refer to
See “Compare Match Output Unit” on page 133.
“Timer/Counter Timing Diagrams” on page
Table 16-3 on page
Figure 16-5 on page
Table 16-5 on page
144. For fast PWM mode, refer to
ATmega165P
135. The counter value
144.
138.
134