PIC18F86J50-I/PT Microchip Technology, PIC18F86J50-I/PT Datasheet - Page 408

• Manufacturer Part Number: PIC18F86J50-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 65
• Ram Memory Size: 3904Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J50 FAMILY
26.2.2
ADDFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39775C-page 408
Q Cycle Activity:
Note:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
EXTENDED INSTRUCTION SET
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
=
=
literal ‘k’
ADDFSR 2, 23h
Add Literal to FSR
ADDFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) + k → FSR(f)
None
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
1
1
Read
1110
Q2
03FFh
0422h
1000
Process
Data
Q3
ffkk
Write to
FSR
kkkk
Q4
ADDULNK
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Operation
Decode
FSR2
PC
FSR2
PC
No
Q1
=
=
=
=
Operation
literal ‘k’
ADDULNK 23h
Add Literal to FSR2 and Return
ADDULNK k
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
None
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
1
2
Read
1110
No
Q2
03FFh
0100h
0422h
(TOS)
© 2009 Microchip Technology Inc.
1000
Operation
Process
Data
No
Q3
11kk
Operation
Write to
FSR
No
kkkk
Q4