PIC18F86J50-I/PT Microchip Technology, PIC18F86J50-I/PT Datasheet - Page 361

• Manufacturer Part Number: PIC18F86J50-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 65
• Ram Memory Size: 3904Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.3.2
When the on-chip regulator is enabled, PIC18F87J10
family devices also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a regulated level, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON<0>).
The operation of the Brown-out Reset is described in
more detail in Section 4.4 “Brown-out Reset (BOR)”
and Section 4.4.1 “Detecting BOR”. The brown-out
voltage levels are specific in Section 28.1 “DC Charac-
teristics: Supply Voltage PIC18F87J50 Family
(Industrial)”.
25.3.3
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
never exceed V
25.3.4
When enabled, the on-chip regulator always consumes
a small incremental amount of current over I
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON<7>, Register 25-9). Setting
this bit disables the regulator in Sleep mode and
reduces its current consumption to a minimum.
FIGURE 25-3:
© 2009 Microchip Technology Inc.
ON-CHIP REGULATOR AND BOR
POWER-UP REQUIREMENTS
OPERATION IN SLEEP MODE
Note 1:
CPU Clock
Peripheral
PLL Clock
Program
Counter
DD
INTRC
Output
OSC1
Clock
by 0.3 volts.
T
OST
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Wake from Interrupt Event
= 1024 T
PC
OSC
; T
Q1
PLL
T
OST
= 2 ms (approx). These intervals are not shown to scale.
DDCORE
(1)
Q2
PC + 2
DD
OSTS bit Set
. This
must
T
Q3
PLL (1)
Q4
PIC18F87J50 FAMILY
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to insure the regu-
lator has enough time to stabilize. The REGSLP bit is
automatically cleared by hardware when a Low-Voltage
Detect condition occurs.
25.4
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an Oscillator Start-up Timer
(OST) delay, Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
Q1
1
Transition
2
Clock
Two-Speed Start-up
n-1 n
oscillator
PC + 4
Q2
mode
Q3 Q4
is
Q1
PC + 6
DS39775C-page 361
Q2
HS
Q3
or
HSPLL