PIC18F86J50-I/PT Microchip Technology, PIC18F86J50-I/PT Datasheet - Page 140

• Manufacturer Part Number: PIC18F86J50-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 65
• Ram Memory Size: 3904Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J50 FAMILY
REGISTER 10-4:
10.2
PORTA is a 6-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA. The
corresponding Output Latch register is LATA.
The RA4 pin is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. It is also multi-
plexed as the Parallel Master Port Data pin. The other
PORTA pins are multiplexed with the analog V
V
Converter inputs is selected by clearing or setting the
control bits in the ANCON0 register.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
OSC2/CLKO/RA6
serve as the external circuit connections for the
external (primary) oscillator circuit (HS and HSPLL
Oscillator modes), or the external clock input (EC and
ECPLL Oscillator modes). In these cases, RA6 and
RA7 are not available as digital I/O and their
corresponding TRIS and LAT bits are read as ‘0’.
DS39775C-page 140
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
REF
Note 1: The RA5 (RA5/PMD4/AN4/C2INA) pin is a
- inputs. The operation of pins RA5:RA0 as A/D
U-0
—
2: RA5 and RA3:RA0 are configured as
PORTA, TRISA and
LATA Registers
multiplexed A/D convertor, Parallel Master
Port data and also a Comparator 2 input A.
(PMP pin placement depends on the
PMPMX Configuration bit.)
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
Unimplemented: Read as ‘0’
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
U-0
and
—
PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1
OSC1/CLKI/RA7
W = Writable bit
‘1’ = Bit is set
U-0
—
REF
normally
+ and
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
For INTOSCx and INTOSCPLLx Oscillator modes
(FOSC2 Configuration bit is ‘0’), either RA7, or both
RA6 and RA7, automatically become available as digi-
tal I/O, depending on the oscillator mode selected.
When RA6 is not configured as a digital I/O, in these
cases, it provides a clock output at F
possible configurations for RA6 and RA7, based on
oscillator mode, is provided in Register 10-3. For these
pins, the corresponding PORTA, TRISA and LATA bits
are only defined when the pins are configured as I/O.
TABLE 10-3:
EXAMPLE 10-1:
(FOSC2:FOSC0 Configuration bits)
INTOSCPLLO (011)
INTOSCPLL (010)
INTOSCO (001)
INTOSC (000)
Legend: CLKO = F
U-0
CLRF
CLRF
BSF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
—
PORTA
LATA
WDTCON,ADSHR ; Enable write/read to
1Fh
ANCON0
WDTCON,ADSHR ; Disable write/read
0CFh
TRISA
Oscillator Mode
port.
U-0
—
FUNCTION OF RA7:RA6 IN
INTOSC AND INTOSCPLL
MODES
OSC
INITIALIZING PORTA
© 2009 Microchip Technology Inc.
; Initialize PORTA by
; clearing output
; data latches
; Alternate method to
; clear
; the shared SFR
; Configure A/D
; for digital inputs
; to the shared SFR
; Value used to
; initialize
; data direction
; Set RA<3:0> as inputs,
; RA<5:4> as outputs
x = Bit is unknown
/4 clock output; I/O = digital
U-0
—
data latches
OSC
CLKO
CLKO
RA6
/4. A list of the
I/O
I/O
PMPTTL
R/W-0
RA7
I/O
I/O
I/O
I/O
bit 0