PIC18F86J50-I/PT Microchip Technology, PIC18F86J50-I/PT Datasheet - Page 292

• Manufacturer Part Number: PIC18F86J50-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 65
• Ram Memory Size: 3904Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J50 FAMILY
FIGURE 20-7:
TABLE 20-6:
20.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RXx/DTx line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
DS39775C-page 292
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Name
Note:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
SSP2IF
SSP2IE
SSP2IP
PMPIF
PMPIE
PMPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
ASYNCHRONOUS RECEPTION
Start
bit
BCL2IE
BCL2IP
BCL2IF
bit 0
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
TMR0IE
DTRXP
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
Bit 5
bit 7/8
Stop
INT0IE
TX1IE
TX1IP
TX2IE
TX2IP
CREN
SYNC
bit
TX1IF
TX2IF
SCKP
Bit 4
Word 1
RCREGx
Start
bit
TMR4IF
TMR4IE
TMR4IP
bit 0
SSP1IE
SSP1IP
ADDEN
SSP1IF
SENDB
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the LIN
protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 20-8) and asynchronously if the device is in
Sleep mode (Figure 20-9). The interrupt condition is
cleared by reading the RCREGx register.
The WUE bit is automatically cleared once a
low-to-high transition is observed on the RXx line
following the wake-up event. At this point, the EUSART
module is in Idle mode and returns to normal operation.
This signals to the user that the Sync Break event is
over.
BRG16
RBIE
Bit 3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
bit 7/8
Word 2
RCREGx
BRGH
FERR
Bit 2
—
Stop
bit
TMR2IF
TMR2IE
TMR2IP
CCP4IE
CCP4IP
CCP4IF
INT0IF
OERR
TRMT
Start
© 2009 Microchip Technology Inc.
WUE
Bit 1
bit
TMR1IF
TMR1IE
TMR1IP
CCP3IE
CCP3IP
CCP3IF
ABDEN
RX9D
TX9D
bit 7/8
RBIF
Bit 0
Stop
bit
on Page:
Values
Reset
61
64
64
64
64
64
64
63
63
63
65
65
65