PIC18F86J50-I/PT Microchip Technology, PIC18F86J50-I/PT Datasheet - Page 154

• Manufacturer Part Number: PIC18F86J50-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 65
• Ram Memory Size: 3904Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J50 FAMILY
TABLE 10-12:
TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39775C-page 154
PORTE
LATE
TRISE
PORTG
Legend: Shaded cells are not used by PORTE.
Note 1:
RE5/AD13/
PMA11/P1C
RE6/AD14/
PMA10/P1B
RE7/AD15/
PMA9/ECCP2/
P2A
Legend:
Note 1:
Pin Name
Name
2:
3:
4:
5:
Unimplemented on 64-pin devices, read as ‘0’.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller
mode).
Default configuration for PMP (PMPMX Configuration bit = 1).
TRISE7
LATE7
RDPU
Bit 7
RE7
ECCP2
Function
AD13
AD14
AD15
PMA10
PMA11
P1C
P1B
P2A
PMA9
PORTE FUNCTIONS (CONTINUED)
RE5
RE6
RE7
(1)
(1)
(4)
(3)
(3)
(3)
(4)
TRISE6
LATE6
REPU
Bit 6
RE6
Setting
TRIS
0
1
x
x
x
0
0
1
x
x
x
0
0
1
x
x
x
0
1
0
RJPU
TRISE5
LATE5
Bit 5
I/O
RE5
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
(1)
Type
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
I/O
ST
ST
ST
ST
TRISE4
LATE4
Bit 4
RG4
RE4
LATE<5> data output.
PORTE<5> data input.
External memory interface, address/data bit 13 output.
External memory interface, data bit 13 input.
Parallel Master Port address.
ECCP1 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<6> data output.
PORTE<6> data input.
External memory interface, address/data bit 14 output.
External memory interface, data bit 14 input.
Parallel Master Port address.
ECCP1 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<7> data output.
PORTE<7> data input.
External memory interface, address/data bit 15 output.
External memory interface, data bit 15 input.
Parallel Master Port address.
ECCP2 compare output and ECCP2 PWM output; takes priority over
port data.
ECCP2 capture input.
ECCP2 Enhanced PWM output, channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
TRISE3
LATE3
Bit 3
RG3
RE3
TRISE2
LATE2
Bit 2
RE2
RG2
Description
TRISE1
LATE1
Bit 1
RG1
RE1
© 2009 Microchip Technology Inc.
(2)
(2)
(2)
TRISE0
LATE0
Bit 0
RG0
RE0
(2)
(2)
(2)
on Page:
Values
Reset
65
64
64
65