TOOLSTICK540DC Silicon Laboratories Inc, TOOLSTICK540DC Datasheet - Page 181

• Manufacturer Part Number: TOOLSTICK540DC
• Description: DAUGHTER CARD TOOLSTICK F540
• Manufacturer: Silicon Laboratories Inc
• Series: ToolStickr
• Type: MCUr

Specifications of TOOLSTICK540DC

• Contents: Daughter Card
• Processor To Be Evaluated: C8051F54x
• Processor Series: C8051F54x
• Interface Type: USB
• Operating Supply Voltage: 2.7 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F54x
• For Use With: 336-1345 - TOOLSTICK BASE ADAPTER336-1182 - ADAPTER USB DEBUG FOR C8051FXXX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1717

LIN Register Definition 19.5. LIN0CTRL: LIN0 Control Register
Indirect Address = 0x08
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
WUPREQ
RSTERR
RSTINT
STREQ
DTACK
SLEEP
Name
STOP
TXRX
STOP
W
7
0
Stop Communication Processing Bit. (slave mode only)
This bit always reads as 0.
0: No effect.
1: Block the processing of LIN communications until the next SYNC BREAK signal.
Sleep Mode Bit. (slave mode only)
0: Wake the device after receiving a Wakeup interrupt.
1: Put the device into sleep mode after receiving a Sleep Mode frame or a bus idle
timeout.
Transmit / Receive Selection Bit.
0: Current frame is a receive operation.
1: Current frame is a transmit operation.
Data Acknowledge Bit. (slave mode only)
Set to 1 after handling a data request interrupt to acknowledge the transfer. The bit
will automatically be cleared to 0 by the LIN controller.
Reset Interrupt Bit.
This bit always reads as 0.
0: No effect.
1: Reset the LININT bit (LIN0ST.3).
Reset Error Bit.
This bit always reads as 0.
0: No effect.
1: Reset the error bits in LIN0ST and LIN0ERR.
Wakeup Request Bit.
Set to 1 to terminate sleep mode by sending a wakeup signal. The bit will automati-
cally be cleared to 0 by the LIN controller.
Start Request Bit. (master mode only)
1: Start a LIN transmission. This should be set only after loading the identifier, data
length and data buffer if necessary.
The bit is reset to 0 upon transmission completion or error detection.
SLEEP
R/W
6
0
TXRX
R/W
5
0
DTACK
R/W
Rev. 1.1
4
0
Function
RSTINT
W
3
0
RSTERR
W
2
0
C8051F54x
WUPREQ
R/W
1
0
STREQ
R/W
0
0
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