MT48H8M32LFB5-10 IT Micron Technology Inc, MT48H8M32LFB5-10 IT Datasheet - Page 54

• Manufacturer Part Number: MT48H8M32LFB5-10 IT
• Description: IC SDRAM 256MBIT 100MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
1. All voltages referenced to V
2. This parameter is sampled. V
3.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured for 1.8V at 0.9V, 2.5V at 1.25V, or 3.3V at 1.65V with equivalent
biased at 0.9V, 1.25V, and 1.4V respectively. f = 1 MHz.
I
with minimum cycle time and the outputs open.
operation over the full temperature range (-40°C ≤ T
ensured.
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sit between V
load:
Test loads with full DQ driver strength. Performance will vary with actual system DQ
bus capacitive loading, termination, and programmed drive strength.
t
a reference to V
High-Z.
point. If the input transition time is longer than
enced at V
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
1.8V option
Q
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
specifications are tested after the device is properly initialized.
is dependent on output loading and cycle rates. Specified values are obtained
DD
current will increase or decrease proportionally according to the amount of
IL
(MAX) and V
IH
20pF
and V
DD
OH
tests have V
or V
IL
2.5/3.3V option
Q
IH
(or between V
OL
IH
or V
t
. The last valid data element will meet
54
SS
SS
T = 1ns.
(MIN) and no longer at the V
t
.
DD
t
WR.
CKS; clock(s) specified as a reference only at minimum
and V
IL
t
WR plus
IL
, V
levels.
and V
DD
SS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q = +1.8V, 2.5V or 3.3V; T
30pF
IL
Q must be at same potential.) The two AUTO
IH
t
and V
RP; clock(s) specified as a reference only at
, with timing referenced to V
IH
) in a monotonic manner.
256Mb: x32 Mobile SDRAM
t
T (MAX), then the timing is refer-
A
≤ +85°C for T
IH
DD
/2 crossover point.
©2003 Micron Technology, Inc. All rights reserved.
and V
A
= 25°C; ball under test
t
REF refresh require-
DD
t
OH before going
A
Q must be pow-
IH
on IT parts) is
/2 = crossover
Notes