MT48H8M32LFB5-8 TR Micron Technology Inc, MT48H8M32LFB5-8 TR Datasheet - Page 9

• Manufacturer Part Number: MT48H8M32LFB5-8 TR
• Description: IC SDRAM 256MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1054-2

Functional Description
Initialization
Register Definition
Mode Register
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
In general, the 256Mb SDRAMs (2 Meg x 32 x 4 banks) are quad-bank DRAMs that oper-
ate at 3.3V, 2.5V, and 1.8V and include a synchronous interface (all signals are registered
on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is orga-
nized as 4,096 rows by 512 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (A0–A8) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections pro-
vide detailed information covering device initialization, register definition, command
descriptions, and device operation.
SDRAMs must be powered up and initialized in a predefined manner. Operational pro-
cedures other than those specified may result in undefined operation. Once the power is
applied to V
defined as a signal cycling within timing constraints specified for the clock ball), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
In order to achieve low power consumption, there are two mode registers in the compo-
nent: mode register and extended mode register. Extended mode register is illustrated in
Figure 5. The mode register is used to define the specific mode of operation of the
SDRAM. This definition includes the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as shown in Figure 3. The mode reg-
ister is programmed via the LOAD MODE REGISTER command and will retain the
stored information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the write burst mode, and M10 and M11 should be set to
zero. M12 and M13 should be set to zero to prevent the extended mode register from
being programmed.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
DD
and V
DD
Q (simultaneously) and the clock is stable (stable clock is
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x32 Mobile SDRAM
Functional Description
©2003 Micron Technology, Inc. All rights reserved.