MT48H8M32LFB5-8 TR Micron Technology Inc, MT48H8M32LFB5-8 TR Datasheet - Page 17

• Manufacturer Part Number: MT48H8M32LFB5-8 TR
• Description: IC SDRAM 256MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1054-2

Commands
Table 7: Truth Table – Commands and DQM Operation
COMMAND INHIBIT
NO OPERATION (NOP)
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or DEEP POWER DOWN
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN
Notes: 1. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
Table 7 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear following "Opera-
tion" on page 21; these tables provide current state/next state information.
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected and the DQ balls tri-state. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
2. A0–A8 provide column address; A10 HIGH enables the auto precharge feature (non persis-
3. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER DOWN when CKE
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks pre-
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
8. A0–A11 define the op-code written to the mode and extended mode register.
9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which
bank is being read from or written to.
is LOW.
mand could coincide with data on the bus. However the DQs column reads a don’t care
state to illustrate that the BURST TERMINATE command can occur when there is no data
present.
charged and BA0, BA1 are “Don’t Care.”
except for CKE.
delay). DQM0 controls DQ0–DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23;
and DQM3 control DQ24–DQ31.
CS# RAS# CAS# WE#
H
X
X
17
L
L
L
L
L
L
L
L
X
H
H
H
H
X
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
X
X
L
L
L
L
X
H
H
H
H
X
X
L
L
L
L
256Mb: x32 Mobile SDRAM
DQM
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
Bank/Row
©2003 Micron Technology, Inc. All rights reserved.
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
X
X
High-Z
Active
Commands
Valid
DQs
X
X
X
X
X
X
X
X
Notes
3, 4
6, 7
1
2
2
5
8
9
9