MT48H8M32LFB5-8 TR Micron Technology Inc, MT48H8M32LFB5-8 TR Datasheet - Page 13

• Manufacturer Part Number: MT48H8M32LFB5-8 TR
• Description: IC SDRAM 256MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1054-2

Operating Mode
Write Burst Mode
Low-Power Extended Mode Register Definition
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 4. Table 5 indicates the operating frequencies
at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The pro-
grammed burst length applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and
WRITE bursts; when M9= 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
The low-power extended mode register controls the functions beyond those controlled
by the mode register. These additional functions are special features of the mobile
device. They include temperature compensated self refresh (TCSR) control, partial array
self refresh (PASR), and output drive strength. Not programming the extended mode
register upon initialization will result in default settings for the low-power features. The
extended mode will default with the temperature sensor enabled, full drive strength, and
full array refresh.
The low-power extended mode register is programmed via the MODE REGISTER SET
command (BA1 = 1, BA0 = 0) and retains the stored information until it is programmed
again or the device loses power.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x32 Mobile SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Register Definition