MT48H8M32LFB5-8 TR Micron Technology Inc, MT48H8M32LFB5-8 TR Datasheet - Page 24

IC SDRAM 256MBIT 125MHZ 90VFBGA

MT48H8M32LFB5-8 TR

Manufacturer Part Number
MT48H8M32LFB5-8 TR
Description
IC SDRAM 256MBIT 125MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48H8M32LFB5-8 TR

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
256M (8Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1054-2
Figure 9: CAS Latency
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
This is shown in Figure 10 for CAS latencies of one, two, and three; data element n + 3 is
either the last of a burst of four or the last desired of a longer burst. The 256Mb SDRAM
uses a pipelined architecture and therefore does not require the 2n rule associated with
a prefetch architecture. A READ command can be initiated on any clock cycle following
a previous READ command. Full-speed random read accesses can be performed to the
same bank, as shown in Figure 10 on page 25, or each subsequent READ may be per-
formed to a different bank.
COMMAND
COMMAND
COMMAND
CLK
CLK
CLK
DQ
DQ
DQ
READ
READ
READ
T0
T0
T0
t
t AC
LZ
CL = 1
24
CL = 2
NOP
NOP
T1
NOP
T1
T1
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t AC
LZ
D
t OH
OUT
CL = 3
T2
NOP
T2
NOP
T2
t
t AC
LZ
256Mb: x32 Mobile SDRAM
D
t OH
OUT
©2003 Micron Technology, Inc. All rights reserved.
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
Operation
T4

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