MT48H8M32LFB5-8 TR Micron Technology Inc, MT48H8M32LFB5-8 TR Datasheet - Page 18

• Manufacturer Part Number: MT48H8M32LFB5-8 TR
• Description: IC SDRAM 256MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1054-2

LOAD MODE REGISTER
ACTIVE
READ
WRITE
PRECHARGE
Auto Precharge
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
The mode register is loaded via inputs A0, BA0, and BA1. (See "Mode Register" on page
9.) The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands
can only be issued when all banks are idle, and a subsequent executable command can-
not be issued until
The values of the load mode register and extended mode register will be retained even
when exiting deep power-down mode.
The ACTIVE command is used to open (or activate) a row in a particular bank for a sub-
sequent access. The value on the BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0–A11 selects the row. This row remains active (or open) for accesses
until a PRECHARGE command is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8 selects
the starting column location. The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be pre-
charged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Read data appears on the DQs subject to the logic
level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH,
the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered
LOW, the DQs will provide valid data.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8
selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be pre-
charged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQs is written to the
memory array subject to the DQM input logic level appearing coincident with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to mem-
ory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored,
and a write will not be executed to that byte/column location.
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank.
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE com-
mand. A precharge of the bank/row that is addressed with the READ or WRITE com-
t
RP) after the precharge command is issued. Input A10 determines
t
MRD is met.
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x32 Mobile SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Commands