MC10XS4200FK Freescale Semiconductor, MC10XS4200FK Datasheet - Page 46

• Manufacturer Part Number: MC10XS4200FK
• Description: Power Switch ICs - Power Distribution 24v 10MOHM DUAL HI-SIDE
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS4200FK

• Rohs: yes
• On Resistance (max): 18 mOhms
• Operating Supply Voltage: 8 V to 36 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-23
• Minimum Operating Temperature: - 40 C

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
ADDRESS 0110 — GLOBAL CONFIGURATION
REGISTER (GCR)
diagnostic functions.See
(PWM_en_1 and PWM_en_0) will activate the internal PWM
function of both channels simultaneously according to the
values of duty cycle and turn-on delays in the PWMR_s and
CONFR_s registers
never be used to drive channels in parallel. To increase the
load current capability, the instructions in the section
Operation
synchronization between both channels). Only configuration
and diagnostic information of bank 0 (A
this setting (see
synchronization between both channels). Only configuration
and diagnostic information of bank 0 (A
this setting (see
sensing mode. When T&H is activated, the value of the
channel’s load current is kept available after turn-off.
function. A logic [0] enables the SPI watchdog.
V
Fail-safe mode after V
sensing options. The CSNS pin outputs a scaled value of the
selected channel’s load current, the sum of both currents or
the die temperature, according to the values in
When the highest over-current range is selected (bit D8 of the
OCR register, HOCR = 0), the device’s CSNS pin will only
output scaled values of a single channel’s load current.
46
Table 22. Current Sense Pin Functionality Selection
10XS4200
DD
D8
0
0
0
1
1
1
1
x
The GCR register is used to activate various functions and
Setting bits D8 = 1 and D7 = 1 of the GCR register
Setting bit D6 will set parallel mode (improved switching
Setting bit D6 will set parallel mode (improved switching
Setting Bit D5 (T_H_en = 1) activates Track & Hold current
Setting bit D4 (WD_dis = 1) disables the SPI watchdog
Setting bit D3 (V
Bits D6 (parallel bit), D2 and D1 set the different (current)
failure detection. When enabled, the device will enter
D6
x
x
x
x
0
x
x
1
should be followed.
D2
0
0
1
1
0
1
1
0
Parallel
Parallel
D1
0
1
0
1
1
0
1
1
DD_FAIL_EN
(Table
disabled
current sensing on channel 0
current sensing on channel 1
temperature sensing
current sensing on channel 0
current sensing on channel 1
temperature
Sensing of summed currents; channels 0
and 1
DD
Operation).
Operation).
Table 9
Activated Function at CSNS Pin
< V
6). However, this option should
DD(FAIL).
= 1) will enable or disable the
0
0
= 0) is available in
= 0) is available in
Table
Parallel
22.
over-voltage protection. Setting this bit to [0] (default), will
enable it.
ADDRESS A
(CALR_S)
calibrated independently. Setting the appropriate calibration
word in the CALR_s register
calibration mode. The default switching frequency is 400 Hz,
but can be changed by applying a specific calibration
procedure. See
bit =
SO REGISTER ADDRESSING
channel-specific SO registers containing the channel’s
configuration and diagnostics status
registers are FAULTR_s, PWMR_s, CONFR_s, OCR_s, and
RETRYR_s.
following common SO-registers: STATR, GCR, and DIAGR.
All the SO registers can be addressed by setting the
appropriate bits in the SI-STATR_s register (bits D13, D2,
D1, D0). The value of the bit D13 determines which register
bank is addressed (bank 0 or 1). Data is made available the
next cycle after register addressing.
the addressed SO register as long as
when the data from the previous SPI cycle was invalid. In this
case, the device outputs the contents of the last successfully
addressed SO register.
SERIAL OUTPUT REGISTER ASSIGNMENT
pin is previously addressed by bits D13, D2, D1, and D0 of
the STATR_s SI register
functional assignment (OD15 : OD0) of each of the thirteen
SO register bits, preceded by the address of the SI STATR_s
required to address it.
Setting bit D0 (OV_dis = 1 of the GCR reg.) will disable
The internal clock frequency of both channels can be
The device has two register banks, each of which has five
Global fault and diagnostic information is contained in the
The output status register correctly reflects the contents of
The output register that will be shifted out through the SO
• Bit OD15 (MSB) reports the state of the watchdog bit
• Bit OD14 (PF, active 1) reports an eventual parity error
• Bits OD13:OD10 echo the state of bits D13, D2, D1, and
• Bit OD9: Normal mode (NM) reports the device state. In
• Bits OD8 : OD0 are the contents of the selected SO
1).
from the previously clocked-in SPI message.
on the previously transferred SI register contents.
D0 (SOA3: SOA0) of the previously received SI word.
Normal Mode, NM = 1.
register (addressed by bit D13 and bits D2 : D0 of the
previous SI STATR register).
0
111 — CALIBRATION REGISTER
Internal Clock & Internal PWM (Clock_int_s
Analog Integrated Circuit Device Data
(Table
(Table
11).
Freescale Semiconductor
11) puts the device in
(Table
Table 22
CSB
is low, except
7). These
gives the