MC10XS4200FK Freescale Semiconductor, MC10XS4200FK Datasheet - Page 29

• Manufacturer Part Number: MC10XS4200FK
• Description: Power Switch ICs - Power Distribution 24v 10MOHM DUAL HI-SIDE
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS4200FK

• Rohs: yes
• On Resistance (max): 18 mOhms
• Operating Supply Voltage: 8 V to 36 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-23
• Minimum Operating Temperature: - 40 C

mode, the FSOB pin returns to logic high and previously set
faults and SPI registers are reset, except bits POR,
PARALLEL and fault bits of latchable faults that had actually
been latched.
FAULT MODE
faults occurs in Normal or Fail-safe mode:
any channel in real time (active low). Additionally, the
assigned fault bit in the STATR_s or FAULTR_s register is
set to one. Conversely to the
until the corresponding register is read, even if the fault has
disappeared. These bits can be read via the SO pin. Fault
occurrence will also result in a turn-off of the incurred
channel, except for the following faults: Open-load (On and
Off state), External Clock Failure and Output(s) shorted to
V
simultaneous turn-off of both channels. Details on the
device’s behavior, after the occurrence of one of the above
faults can be found in
when:
Resetting FAULT bits
channel-specific fault information. Reading the register the
fault bit is contained in, will clear it, provided a failure cause
disappearance has been detected and the fault wasn’t
latched.
Fault/Fail-safe mode. and behaves according to the
description of fault mode. However, SPI registers remain
reset and can not be accessed. Only the Direct inputs control
the channels.
Returning from Fault Mode to Fail-safe Mode
Fail-safe mode has been detected, the device returns to Fail-
Analog Integrated Circuit Device Data
Freescale Semiconductor
Entering Fault Mode from Fail-safe Mode
PWR
The device enters Fault mode when any of the following
• Over-temperature fault, (latchable fault)
• Over-current fault, (latchable fault)
• Severe short-circuit fault, (latchable fault)
• Output shorted to V
• Open-load fault in OFF state (default: disabled)
• Open-load fault in ON state (default: disabled)
• External clock failure (default: enabled)
• Over-voltage fault (enabled by default)
• Under-voltage fault, (latchable fault)
The Fault Status pin (
Fault mode
• V
• wake-up = 1, and
• fail-safe = X, and
• fault = 1 (see
Registers STATR_s and FAULTR_s contain global and
When a Fault occurs in Fail-safe mode, the device is in
When disappearance of the fault previously produced in
Sleep
. Under and over-voltage occurrences will cause
PWR
(+V
Mode)
(Operation and Operating
DD
) were within the normal voltage range, and
Going from Normal to Fail-safe, Fault or
Protection and Diagnostic
FSB)
PWR
FSB
in OFF state (default: disabled)
asserts a fault occurrence on
pin, a fault bit remains set
Modes) is entered
Features.
safe mode and behaves accordingly. FSB goes high, but the
auto-retry counter is not reset. Latched faults are not
delatched. SPI registers remain reset.
LATCHABLE FAULTS
device responds to the so-called latchable faults. Latchable
faults are: over-current (OC), severe short-circuit (SC), over-
temperature (OT), and under-voltage (UV). If a latchable fault
occurs, the channel is turned of, the
the assigned fault bit is set. These bits can not be reset
before the next turn-on event is generated by auto-retry.
Next, the channel will automatically be turned on at a
programmable interval, provided auto-retry was enabled and
the channel wasn’t latched.
available number of auto-retries, the
returns to logic [1], but the fault bit remains set. It can still be
reset by reading out the SPI register in which it is contained.
hasn’t disappeared at the first turn-on event following
expiration of the available amount of auto-retries (see
retry). In that case, the channel gets latched and the
remains low. The fault bit can only be reset by reading out the
associated SPI register, after having performed a delatch
sequence
Fault Delatching
again, a delatch sequence must execute after the
disappearance of the failure cause. Delatching will also allow
to reset the fault bit of latched faults (see
bits). To reset the
channels’ fault control signal fc[x] (generating a 1_0_1
sequence), or by resetting the auto-retry counter (provided
retry is enabled). See
Delatching then actually occurs at the rising edge of the turn-
on event.
internal logic circuitry to control the diagnostic functions. The
value of fc[x] depends on the state of the variables IN_ON[x],
DIR_dis[x] and ON[x] and is expressed as follows:
according to the way the user controls the device.
• In direct-input controlled mode (DIR_dis_s = 0), the IN[x]
• In SPI-controlled mode, the ON_bit state (D8 of the
auto-retry sequence (before latching) allows turning the
channel on unconditionally.
fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1)
An auto-retry function (see Auto-retry) controls how the
If the failure disappears prior to the expiration of the
However, the fault actually gets latched if the failure cause
To delatch a latched channel and be able to turn it on
Delatching is achieved by either alternating the state of the
Signal fc[x] is an internal signal used by the device’s
Alternating the fc[x] signal (by) is achieved differently
pin must be set low, remain low for at least t
and set high again (be switched On). This might happen
automatically when operating at frequencies, f<4.0 Hz.
PWMR_s reg.) must be alternated (‘toggled’). No minimum
OFF state duration is required in this case.
Performing a delatch sequence anytime during an ongoing
(Fault
Delatching).
FSB
Reset of the Auto-retry
pin, both channels must be delatched.
OPERATION AND OPERATING MODES
FUNCTIONAL DEVICE OPERATION
FSB
FSB
pin goes low, and
Resetting FAULT
pin automatically
Counter).
IN
seconds,
10XS4200
FSB
Auto-
pin
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