MC10XS4200FK Freescale Semiconductor, MC10XS4200FK Datasheet

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... V and 5.0 V compatible 16-bit SPI port for device control, configuration and diagnostics at rates up to 8.0 MHz V DD MCU GND * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2012. All rights reserved. MC10XS4200FK 10XS4200 VDD VPWR I/O CLOCK ...

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... Detect. Temperature Feedback GND Figure 2. Internal Block Diagram VPWR Drain/Gate Charge Clamp Pump Selectable Slew Rate Gate Driver HS0 Short-circuit to VPWR detec. Open-load Detect HS0 HS1 HS1 Output Current Sense Analog MUX CSNS SYNC Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Functional Internal Block Description Functional Device Operation Operation and Operating Modes Protection and Diagnostic Features Logic Commands and SPI Registers Typical Applications Soldering Information Packaging Revision History Analog Integrated Circuit Device Data Freescale Semiconductor TABLE OF CONTENTS TABLE OF CONTENTS ...

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... This input pin is connected to the SPI chip-select output of an external micro- Chip Select controller. CSB is internally pulled (Active Low) SYNC GND VPWR Definition Functional Fault Mode current source Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... SYNC Output Output Current Synchronization Analog Integrated Circuit Device Data Freescale Semiconductor Functional Description This input pin connected to an external SPI Clock signal. The SCLK Serial Clock pin is internally connected to a pull-down current source I This input pin receives the SPI input data from an external device (micro- Serial Input controller or another extreme switch device in case of daisy-chaining) ...

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... ESD2 ± 750 ESD3 ± 500 ESD4 = 150 °C initial PWR J = 125 °C initial <2.0 Hz). PWR 125 °C initial <2.0 Hz). PWR 1500 Ω), and the Charge Device ZAP Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Analog Integrated Circuit Device Data Freescale Semiconductor Symbol T T ...

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... V) before the end of the auto-retry period PWR , under-voltage is detected see Under-voltage Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Power Supply): High slew rate selected Medium slew rate selected: Low slew rate selected: Over-current Detection thresholds with CSNS_ratio bit = 0 (CSR0) Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR ° & ...

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... C (I defined above, see SRx , _LOAD_ERR_SYS I / CSR - I = CSNS x _LOAD_ERR_SYS (see Activation and Use of Offset Compensation). Analog Integrated Circuit Device Data Freescale Semiconductor – ...

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... See note , but with I obtained after compensation of I CSNS_MEAS Further accuracy improvements can be obtained by performing point calibration. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR ° & PWR ...

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... C (I defined above, see SRx , _LOAD_ERR_SYS I / CSR - I = CSNS x _LOAD_ERR_SYS (see Activation and Use of Offset Compensation). Analog Integrated Circuit Device Data Freescale Semiconductor % % % ...

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... Pins CONF[0:1] are connected to an internal current source, connected itself to an internal voltage regulator (V 26. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1], and CLOCK pins. This parameter is guaranteed by the manufacturing process but is not tested in production. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR ° ...

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... V & PWR Symbol V SOH V SOL I SO(LEAK) R CONF ≤ 125 °C, GND = 0 V. Typical values are A = 5.0 V, unless specified otherwise. DD Min Typ Max Unit V -0.4 – – DD – – 0.4 μA - 2.0 0.0 2.0 kΩ 1.0 – – Infinite Analog Integrated Circuit Device Data Freescale Semiconductor V V ...

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... Typ Max Unit V/μs 0.164 – 0.65 0.28 – 0.79 0.34 – 0.90 V/μs 0.081 – 0.32 0.14 – 0.395 0.17 – 0.45 V/μs 0.29 – 1.30 0.55 – 1.58 0.68 – 1.80 0.75 1.0 1.2 V/μs -0.1 0.0 +0.1 -0.06 0.0 +0.06 -0.14 0.0 +0.14 32 – 128 59 – 245 18 – 68 -25 0.0 25 -50 0.0 50 -13 0.0 13 Figure 4). Analog Integrated Circuit Device Data Freescale Semiconductor μs μs μs μs μs μs ...

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... Figure 4). PWR ) are defined for a stepped SYNREAD_xx A_0 CSNS_ _ = 0). (see X FOR RATIO S Analog Integrated Circuit Device Data Freescale Semiconductor μs μs μs μs μs μs μs μs μs µs µs µ ...

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... Watchdog Timeout for entering Fail-safe Mode due to loss of SPI contact Auto-Retry Repetition Period (when activated): Auto_period bits = 00 Auto_period bits = 01 Auto_period bits = 10 Auto_period bits = 11 Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR °C & V ...

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... FEED (37) T FEED_ERROR (37) T FEED_ERROR _CAL ≤ 125 °C, GND = 0 V. Typical values are A = 5.0 V, unless specified otherwise. DD Min Typ Max Unit 110 125 140 918 1078 1238 10.7 11.1 11.5 mV/°C -15 – +15 -5.0 – +5.0 Analog Integrated Circuit Device Data Freescale Semiconductor °C mV °C °C ...

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... For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (V ceramic speed-up capacitors in parallel with the >8.0 kΩ input resistors are required on pins SCLK, SI, SO, and CS. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T ...

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... V PWM t t DLY_xx DLY_xx ( DLY(ON) DLY(OFF Bulb profile: CONFs = 0 (V (pin 5/6) <0.8 V). Static over-current protection profile activated once per turn-on. Default levels shown as solid lines Time Time PWR 50%V PWR Time F Time Time Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... DD t ENBL t WRSTB CSB 10 LEAD 90 10 SCLK 90% V Don’t Care SI 10% V Figure 7. Timing Requirements During SPI Communication Analog Integrated Circuit Device Data Freescale Semiconductor t OCM2_M t OCM1_M t OCH2 t OCH1 WSCLKh t t SI(SU) WSCLKl t SI(HOLD) DD Must be Valid Don’t Care ...

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... DD t SO(DIS) turn-on turn-off control control (from IN_s or CSB) (from IN_s or CSB) See Figure 3 ) synchronous Mode t FSI 50%V PWR Time t DLY_xx DLY(OFF Track & Hold Mode Time Time Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... V . The CSNS pin can source currents up to about CL(CSNS) 5.6 mA. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION Current sensing with an adjustable ratio is available on both channels, allowing both high-current (bulbs) and low- current (LED) monitoring. By activating the Track & Hold ...

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... Figure 6 and Figure 8) UP logic [1] state). When is CSB CSB DWN Figure 7), starting with bit D15 Table 10. Register addresses and Table 11. The SI pin is . DWN derived voltage, PWR pin becomes CSB must be present DD Table 22. Analog Integrated Circuit Device Data Freescale Semiconductor . ...

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... The device can be configured to control the output switches in parallel, which guarantees good switching synchronization. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL INTERNAL BLOCK DESCRIPTION FAIL-SAFE OUTPUT (FSOB) This pin (active low) is used to indicate loss of SPI communication or loss of SPI supply voltage, V drain output requires an external pull-up resistor to VPWR ...

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... DD Table 4. (Internal Clock & Internal PWM 1)). Frequency, slew rate, duty-cycle, and /2 and “Off” PWR /2. The channel’s switching state PWR when the channel is set to Off PWR Analog Integrated Circuit Device Data Freescale Semiconductor ) FAULT ...

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... RSTB or IN_ON[0] or IN_ON[1] • fail-safe = (V Failure and V _FAIL_en) or (SPI DD DD watchdog timeout (t ) and WD WDTO • fault = OC[0:1] or OT[0:1] or SC[0: (OV and OV ) _DISB Analog Integrated Circuit Device Data Freescale Semiconductor Table 5. Device Operating Modes Wake-up Mode /2 PWR /2 PWR Sleep Normal and V PWR DD Fail-safe Modes) ...

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... Next, a second data word must be received within the timeout period (t change any SPI register contents. Upon entering Normal Normal Failure and V _FAIL_en=1 before and WD_dis = 0). RSTB pin. Thereafter, the device = 310 ms typ. WDTO , = 310 ms typ.), to be able to WDTO Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... When disappearance of the fault previously produced in Fail-safe mode has been detected, the device returns to Fail- Analog Integrated Circuit Device Data Freescale Semiconductor safe mode and behaves accordingly. FSB goes high, but the auto-retry counter is not reset. Latched faults are not delatched. SPI registers remain reset. ...

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... PWM clock periods Table 6 apply. When an external CLOCK(LOW) module). Calibration of the default reduces its maximum variation from about Table 11). Next, the device sets the new value pin and the CSB CSB pin (t ). Then it changes the CSB Analog Integrated Circuit Device Data Freescale Semiconductor or f> ...

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... D6-D8 of the CONFR_1 register (configuration Open- Analog Integrated Circuit Device Data Freescale Semiconductor load/Output short-circuited diagnostics recommended to disable the off-state open-load for the HS1 output. After setting PARALLEL=1, contents of SO registers in bank 0 are copied to the registers of bank 1 only when new information is written in them ...

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... Type of Load resistive: CONF = 0, Lighting mode inductive: CONF = 1, DC motor mode ). OCM2_L Window Activity , I and I _OCH _OCM _OCL Figure 5. This profile has The width of the OCH1 OCH2 or t (see Table 17). OCM1_L OCM2_L Analog Integrated Circuit Device Data Freescale Semiconductor , ...

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... Figure 14. Over-current Shutdown in PWM Mode (solid line) and Non-PWM Mode (dashed line) Analog Integrated Circuit Device Data Freescale Semiconductor Reset of the Duration Counter Reset of the duration counter is achieved by performing a delatch sequence (CONFs = 0), this counter is also reset automatically at each auto-retry (but not in DC motor mode) ...

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... IN[x] input(s) are tied to VPWR. Fail-Safe will be entered under the following conditions: Table 3. Coupling V DS( CLA M P K.I z HS[ IMEG Load V CL GND PWR PWR in case they are connected to V PWR PWR (Figure 21). DD Analog Integrated Circuit Device Data Freescale Semiconductor . ...

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... If V wasn’t set before V DD_FAIL_EN Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES was lost, the device remains SPI-controlled, even though the SPI registers can’t be read. No current will flow from the VPWR to the VDD pin ...

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... In case the device was configured for an unlimited amount of auto-retries (Retry-unlimited_s = 1), auto-retry will (Open-loadOFF = Latched OFF Auto-retry Loop (Open-loadON = 1) ( Retry_s bit auto-retry 0 enabled 1 disabled 0 disabled 1 enabled ) is set through the SPI AUTO Table Analog Integrated Circuit Device Data Freescale Semiconductor 21). ...

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... PWM), on the current sense ratio and on the Analog Integrated Circuit Device Data Freescale Semiconductor optional activation of the open-load in On state detection example, in direct input ( (CSR1), OLON, OLOFF, and OS detection are performed for ...

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... Current 17) selected by the CSNS_ratio bit in the Figure 18. The amount of current the CSNS .The CSNS pin must be CSNS,MAX. 21). Current sensing will operate for load (SYNC)). After turn-off, the Current Sense (SYNC)). However, at the switch-off instant, Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Compensation of the random offset error is achieved by computing the average of both. When a dedicated bit called Offset Positive (OFP = bit D8 of the RETRYR_s register) is set to 1, the Analog Integrated Circuit Device Data Freescale Semiconductor current sunk through the CSNS pin (I by: I =CSR ...

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... It withstands electric fields up to 200 V/m and bulk current injection (BCI 200 mA per ISO11452. The device meets Class 5 of the CISPR25 emission standard. (pin #14, see Figure 3). The OTWAR . OTWAR /2). When supply PWR (seeFactors State). (Figure 21). Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... When Chip Select occurs (1-to-0 transition on the pin), the output register data is clocked out of the SO pin Analog Integrated Circuit Device Data Freescale Semiconductor or 3.3 V CMOS logic levels. Parity check is performed after transfer of each 16-bit SPI data word.The SPI interface can be driven without series resistors provided that voltage ...

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... SOA1 PWM3_s PWM2_s PWM1_s PWM0_s s SR0_s DELAY2_s DELAY1_s DELAY0_ tOCM_s OCH_s OCM_s OCL_s 0 Auto_period Auto_period Retry_unli retry_s 1_s 0_s mited_s CSNS1_en CSNS0_en OV_dis DD_FAIL_en 5.0 V and before DD DD_FAIL_EN Analog Integrated Circuit Device Data Freescale Semiconductor D0 SOA0 ...

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... Table 13. Value of bit A Required for Addressing 0 Register Banks Value A (D13 channel 0 (default channel 1 Analog Integrated Circuit Device Data Freescale Semiconductor SO Returned Data OD8 OD7 OD6 OD5 OD4 ...

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... _OCL1 _OCL2 _OCL3). stands for _OCxy_z Over-current Detection (CSR0). when _OCL3 (Table 16). Current Sense Ratio 0 CRS0 (default) 1 CRS1 and t ), and also OCH_s OCM_s Table OCH1 OCM1_L Table 17). Analog Integrated Circuit Device Data Freescale Semiconductor ) _OCL _OCL2 17 ...

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... Table 19. OCM Current Threshold Selection OCM_s (D1) OCM current threshold 0 OCM1_s (default) 1 Bit D0 (OCL_s) and D8 (HOCR) set the value of the lowest over-current threshold accordingly, as shown in Analog Integrated Circuit Device Data Freescale Semiconductor and I as Table 20. OCL Current Threshold Selection _OCH _OCL) , HOCR (D8) OCM1_M ...

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... D13 and bits the previous SI STATR register). 111 — CALIBRATION REGISTER 0 (Table 11) puts the device in Internal Clock & Internal PWM (Clock_int_s (Table 7). These is low, except CSB (Table 11). Table 22 gives the Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Latched can only be delatched by the procedure described in faults Fault Delatching. Analog Integrated Circuit Device Data Freescale Semiconductor = 0000 (STATR) The FAULTR_s register is reset when it is read out, 0 provided that the failure cause has disappeared and latched faults had been delatched. ...

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... IN1 FSOB SCLK CSB RSTB SI 1 <5.0 k CONF0 75 k CONF1 SYNC CSNS External Control Circuitry direct controls (pedals, handles, etc.) V PWR VPWR 100 nF 1.0 µF HS0 10XS4200 22 nF LOAD 0 HS1 LOAD 1 GND Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... I/O I/O 1.0 k 470 pF MCU 1.0 k SCLK 1 1.9 k I/O 1 1.0 k I/O A/D GND VPWR Figure 22. Two Channels in Parallel / Recommended External Current Sense Circuit Analog Integrated Circuit Device Data Freescale Semiconductor µ PWR DD VDD 100 k 100 nF 1.0 k CLOCK FSB IN0 IN1 FSOB SCLK CSB RSTB ...

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... SOLDERING INFORMATION The 10XS4200 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board. 10XS4200 50 PACKAGING SOLDERING INFORMATION The AN2467 provides guidelines for Printed Circuit Board design and assembly. Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... For the most current package revision, visit below. Dimensions shown are provided for reference only. Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGE DIMENSIONS www.freescale.com and perform a keyword search using the 98ASA00428D listed FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A PACKAGING PACKAGE DIMENSIONS ...

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... PACKAGING PACKAGE DIMENSIONS 10XS4200 52 FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A PACKAGING PACKAGE DIMENSIONS 10XS4200 53 ...

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... PACKAGING PACKAGE DIMENSIONS 10XS4200 54 FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A PACKAGING PACKAGE DIMENSIONS 10XS4200 55 ...

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... PACKAGING PACKAGE DIMENSIONS 10XS4200 56 FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A PACKAGING PACKAGE DIMENSIONS 10XS4200 57 ...

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... PACKAGING PACKAGE DIMENSIONS 10XS4200 58 FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... REVISION DATE DESCRIPTION OF CHANGES 4/2012 • Initial release 1.0 • Updated the values in 6/2012 2.0 • Updated the values in Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY Table 4, Dynamic Electrical Characteristics E SR1_ERR REVISION HISTORY PACKAGE DIMENSIONS 10XS4200 59 ...

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