MC10XS4200FK Freescale Semiconductor, MC10XS4200FK Datasheet - Page 30

• Manufacturer Part Number: MC10XS4200FK
• Description: Power Switch ICs - Power Distribution 24v 10MOHM DUAL HI-SIDE
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS4200FK

• Rohs: yes
• On Resistance (max): 18 mOhms
• Operating Supply Voltage: 8 V to 36 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-23
• Minimum Operating Temperature: - 40 C

FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
of VDD and Power-on-Reset
also delatched and faults are reset.
becomes 1) during operating in Fault mode (fault=1,
failsafe=0), previously latched faults are delatched and SPI
register content is reset (except bits POR & PARALLEL). The
device is then in a combined Fail-safe/Fault mode.
failsafe=1) and (new) faults occurs, the internal auto-retry
counter will not be reset and latched channels will not be
delatched until a delatching sequence has been performed
(seeProtection and Diagnostic
PROGRAMMABLE PWM MODULE
activated by setting PWM_en_s. It modulates an internal or
external clock signal. Setting Clock_int_s = 1 (bit D6 of the
OCR_s register) activates the internal clock, and setting
Clock_int_s = 0 activates the external clock. The duty cycle
can be set in a range from 0 to 100% with 8 bit-resolution
(Table
(Table
clock frequency divided by 256 in internal clock mode, and by
256 or 512 in external clock mode.
.
other
improve EMC performance. Switch-On delay can be selected
among seven different values (default=0) by setting bits
D2…D0 of the CONFR_s register (expressed as a number of
ext./int. PWM clock periods). To start the PWM function at a
30
10XS4200
CLOCK
IN_x
CS
When a Power-ON event occurs (see
When Fail-safe mode is entered (fault=1, fail-safe
When the device was already in Fail-safe mode (fault=1,
Each channel has a fully independent PWM module
By delaying the activation of one channel relative to the
Table 6. PWM Duty Cycle Value Assignment
Figure 12. Internal and External Clock Operation
Internal Clock
Frequency Monitoring
(Table
Calibration
Oscillator
6) by setting bits D8…D0 of the PWMR_s register
11). The channel’s switching frequency equals the
Internal
ON-bit
External Clock
0
1
1
1
1
1
7), switch-on surges can be delayed, which may
÷
(1 + PR_x)
PR_x
Duty Cycle
00000000
00000001
00000010
11111111
X
n
CLOCK_sel_x
CLOCK_fail
Software Configurable
(POR)), latched channels are
÷
PWM ((n+1)/256 duty cycle)
Features).
256
Channel Configuration
PWM (1/256 duty cycle)
PWM (2/256 duty cycle)
PWM (3/256 duty cycle)
PWMR_s register
PWM
Mode
PWM_en_x
fully ON
Loss of VPWR
OFF
Driver
HS_x
Block
VPWR
,
Loss
HSx
known point in time, the PWM_en_s bit (D8 /D7 of the GCR
reg.) must only be set to 1 after having set the PWMR_s (duty
cycle) and CONFR_s (delay) registers. The best way to
optimize EMC is to use an external clock with a staggered
switch on delay.
External Clock & Internal PWM (CLOCK_int_s = 0)
by setting bit D6 =0 of the OCR_s register (Clock_int_s). Duty
cycle values specified in
clock is used, the value of frequency division (256 when
PR[x] = 0) may be doubled by setting the prescaler bit
PR[x]) = 1(bit D7 of the OCR_s reg.). This allows driving the
channels at different switching frequencies from a single
clock signal. Simultaneously setting PWM_en_1=1 and
PWM_en_0=1 will synchronize the channels.
external clock (CLOCK_int_s = 0) and pulse width
modulation (PWM_en_s = 1) are both selected. If a clock
failure occurs under these conditions (f< f
f
fault is detected (FSB =0, CLOCK_fail bit is set (OD2 in the
DIAGR register). The state of the ON_s bit in the SPI register
then determines the channel’s switching state. To return to
external clock mode (and reset FSB), the clock-fail bit must
be read and the external clock has to be within the authorized
range again.
Internal Clock & Internal PWM (Clock_int_s bit = 1)
external microcontroller), the period of each of the internal
PWM clocks can be changed or calibrated (see
Programmable PWM
period = 1/f
+/-30 percent to +/- 10%. The programming procedure is
activated by sending a dedicated word to the SI-CALR
register (see
of the switching period in 2 steps. First it measures the time
elapsed between the first falling edge on the
next rising edge on the
value of the internal clock period accordingly. The actual
Table 7. Switch-on Delay in PWM Mode
CLOCK(HIGH)
The channels can be controlled by an external clock signal
The clock frequency on the CLOCK pin is monitored when
By using a reference time slot (usually available from an
Delay Bits
000
001
010
011
100
101
110
111
PWM(0)
), the external clock signal will be ignored and a
Table
reduces its maximum variation from about
11). Next, the device sets the new value
module). Calibration of the default
Analog Integrated Circuit Device Data
CSB
Table 6
pin (t
128 PWM clock periods
160 PWM clock periods
192 PWM clock periods
224 PWM clock periods
32 PWM clock periods
64 PWM clock periods
96 PWM clock periods
Switch-On Delay
apply. When an external
CSB
Freescale Semiconductor
no delay
). Then it changes the
CLOCK(LOW)
CSB
pin and the
or f>