MC10XS4200FK Freescale Semiconductor, MC10XS4200FK Datasheet - Page 26

• Manufacturer Part Number: MC10XS4200FK
• Description: Power Switch ICs - Power Distribution 24v 10MOHM DUAL HI-SIDE
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS4200FK

• Rohs: yes
• On Resistance (max): 18 mOhms
• Operating Supply Voltage: 8 V to 36 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-23
• Minimum Operating Temperature: - 40 C

FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
each of which can be controlled independently. The device
has four fundamental operating modes: Sleep, Normal, Fail-
safe, and Fault mode, as shown in
Normal mode: by a signal on the Direct Input pin, by an
internal clock signal (autonomous operation) or by an
external clock signal. For bidirectional SPI communication, a
second supply voltage is required (V
When only the direct inputs IN[x] are used, V
DEVICE START-UP SEQUENCE
predictable behavior, the device must undergo a wake-up
sequence. However, it should not be woken up earlier than
the moment at which V
threshold, V
failure threshold, V
port, the device is typically put in wake mode by setting
RSTB=1. Wake-up of applications with direct input control
can be achieved by having signals IN_ON[0] = 1 or
IN_ON[1 ]= 1 (see
contents are reset and Normal mode is entered (as defined in
Table 11
available 50 µs later (typically).
up, its configuration may be undetermined and correct
operation is not guaranteed. In situations where the above
described start-up sequence can not be performed, it is
recommended to generate a wake-up event after the moment
V
CHANNEL CONFIGURATION THROUGH THE SPI
Setting the Channel Configuration
the pulse-width (PWMR_s), the configuration (CONFR_s)
and the over-current (OCR_s) registers. They allow setting,
among others, the following parameters: duty-cycle, delay,
Slew Rate, PWM enable (PWM_en), clock selection
(CLOCK_sel), prescaler (PR), and direct_input disable
(DIR_dis). Extension “_s” means that these registers exist for
each of both channels. Function assignment is described in
detail in the section
Reading Back the Channel’s Status and Settings
Off, normal/fault) are all contained in the STATR register (see
Table
the FAULTR_s and STATR registers. The channel’ settings
(channel configuration) can be read back by reading the
26
10XS4200
PWR
The device possesses two high side switches (channels)
Each channel can be controlled in three different ways in
To put the device in a known configuration and guarantee
If the start-up sequence is not performed at device start-
The channel configuration is determined by the contents of
The channel’s global switching and operating states (On/
has reached the under-voltage threshold.
15). The precise fault type can be found by reading out
and
PWR
Table
(UV), and V
Figure
DD
SI Register Addressing
22). All the device functions will be
(FAIL). In applications using the SPI
PWR
10). After wake-up, all SPI register
has exceeded its under-voltage
DD
has exceeded its supply
Table
DD
FUNCTIONAL DEVICE OPERATION
= 5,0 V or 3.3 V).
OPERATION AND OPERATING MODES
5.
DD
isn’t required.
PWMR, CONF, OCR, RETRY, GCR, and DIAG registers. For
more information, see
NORMAL MODE
either by driving the device through the direct inputs IN[x], or
by establishing SPI communication (requires RSTB =high).
Bidirectional SPI communication additionally requires the
presence of V
communication must take place regularly (see
Maintaining Normal
(NM) when:
Channel Control in Normal Mode
basically follows the logic state of the direct input signal with
the turn-on delay and slew rate specified in
an internal clock signal
(Clock_int_s bit =
turn-on delay are programmable independently for both
channels.
controls the output's PWM frequency, but slew rate, duty
cycle, and turn-on delay are still programmable.
Factors Determining the Channel’s Switching State
instantaneous value of the output voltage. It is defined as
“On” when the output voltage V(HS[x]) > V
when V(HS[x]) < V
should not be confused with the device’s internal channel
control state hson[x] (= High Side On). Signal hson[x] defines
the targeted switching state of the channel (On/Off). It is
either controlled by the value of the direct input signal or by
that of the internal/external clock signals combined with the
SPI register settings. The value of hson[x] is given by the
following boolean expression:
Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and
PWM_en[x] = 0)].
the duty cycle, set by bits D7…D0 of the PWMR register
(Table
from the control signal’s state in the following cases:
• short circuits to GND, before automatic turn-Off (t < t
• short circuits to V
Normal mode (bit NM = 1) can be entered in two ways,
• V
• wake-up = 1, and
• fail-safe = 0, and
• fault = 0.
In direct input mode, the channel’s switching state (On/Off)
In internal clock mode, the switching state is controlled by
In external clock mode, the frequency of the external clock
The switching state of a channel is defined by the
hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and
In this expression Duty_cycle[x] represents the value of
PWR
6). The channel’s actual switching state may differ
(and V
DD
. To maintain the device in Normal mode,
1)). Frequency, slew rate, duty-cycle, and
DD
PWR
Mode). The device is in Normal mode
PWR
) are within the normal range and
Serial Output Register
Analog Integrated Circuit Device Data
(Internal Clock & Internal PWM
/2. The channel’s switching state
when the channel is set to Off
Freescale Semiconductor
PWR
Table
Assignment.
Entering and
/2 and “Off”
4.
FAULT
)