MC10XS4200FK Freescale Semiconductor, MC10XS4200FK Datasheet - Page 41

• Manufacturer Part Number: MC10XS4200FK
• Description: Power Switch ICs - Power Distribution 24v 10MOHM DUAL HI-SIDE
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS4200FK

• Rohs: yes
• On Resistance (max): 18 mOhms
• Operating Supply Voltage: 8 V to 36 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-23
• Minimum Operating Temperature: - 40 C

SPI PROTOCOL DESCRIPTION
transfer over four I/O lines: Serial Input (SI), Serial Output
(SO), Serial Clock (SCLK), and Chip Select (
pins of the device follow a first-in first-out (D15 to D0)
protocol. Transfer of input and output words starts with the
most significant bit (MSB). All inputs are compatible with 5.0
SERIAL INPUT COMMUNICATION PROTOCOL
communication is accomplished with 16-bit messages. A
valid message must start with the MSB (D15) and end with
the LSB (D0)
interpreted according to
watchdog bit (WDIN). Bit D14, Parity check (P), must be set
such that the total number of 1-bits in the SPI word is even
(P=0 for an even number of 1-bits and P=1 for an odd
number). Bank selection is done by setting bit D13. Bits
D12: D10 are used for register addressing. The remaining ten
bits, D9 : D0, are used to configure the device and activate
diagnostic and protective functions. Multiple messages can
be transmitted for applications with daisy chaining (or to
validate already transmitted data) by keeping the
logic 0. Messages with a length different from a multiple of 16
or with a parity error will be ignored. The device has thirteen
input registers for device configuration and thirteen output
registers containing the fault/device status and settings.
Table 11
with extension “_s” refer to functions that have been
implemented independently for each of both channels.
SERIAL PORT OPERATION
pin), the output register data is clocked out of the SO pin
Analog Integrated Circuit Device Data
Freescale Semiconductor
The SPI interface offers full duplex, synchronous data
SPI communication requires that RSTB = high. SPI
When Chip Select occurs (1-to-0 transition on the
gives the SI register function assignment. Bit names
SCLK
CSB
SO
SI
(Table
Notes
D15
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
21). Incoming messages will be
1. RSTB must be in a logic [1] state during data transfer.
2. Data enter the SI pin starting with D15
3. Data are available on the SO pin starting with bit 0D15
D14
Table
D13
11. The MSB, D15, is the
D12
LOGIC COMMANDS AND SPI REGISTERS
Figure 20. 16-Bit SPI Interface Timing Diagram
D11
CSB
).The SI / SO
D10
CSB
CSB
pin at
D9
D8
(MSB) and ending with bit
D7
or 3.3 V CMOS logic levels. Parity check is performed after
transfer of each 16-bit SPI data word.The SPI interface can
be driven without series resistors provided that voltage
ratings on V
Unused SPI-pins must be tied to GND, eventually by resistors
(see
(MSB-first) at the serial clock frequency (SLCK). Bits at the SI
pin are clocked in at the same time. The first sixteen SO
register bits are those addressed by the previous SI word (bit
D13, D2…D0 of the STATR_s input register). At the end of
the chip select event (0-to-1 transition), the SI register
contents are latched. The second SPI word clocked out of the
Serial Output (SO) after the first
initial SO register contents. This allows daisy chaining and
data integrity verification.
event (0-to-1 transition). If it is valid (multiples of 16, no parity
error), the data is latched into the selected register. After
latch-in, the SO pin is tri-stated and the status register is
updated with the latest fault status information.
Daisy Chain Operation
connected in series. The commands enter the device at the
SI pin and leave it by the SO pin, delayed by one command
cycle of 16 bits. To address a particular device in a daisy
chain, the CSB pin of all the devices in that chain has to be
kept low until the SPI message has arrived at its destination.
Once the command has been clocked in by the addressed
device, it can be executed by setting CSB =1.
The message length is validated at the end of the
Daisy-chaining propagates commands through devices
Device Ground
D6
(MSB) and ending with bit 0
D5
DD
and SPI pins
D4
LOGIC COMMANDS AND SPI REGISTERS
Loss).
D0.
D3
FUNCTIONAL DEVICE OPERATION
(Table
D2
CSB
2) aren’t exceeded.
D1
event represents the
(OD0).
D0
10XS4200
CSB
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