MC10XS4200FK Freescale Semiconductor, MC10XS4200FK Datasheet - Page 31

• Manufacturer Part Number: MC10XS4200FK
• Description: Power Switch ICs - Power Distribution 24v 10MOHM DUAL HI-SIDE
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS4200FK

• Rohs: yes
• On Resistance (max): 18 mOhms
• Operating Supply Voltage: 8 V to 36 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-23
• Minimum Operating Temperature: - 40 C

value of the channel’s switching period is obtained by
multiplying the internal clock period by 256.
predefined time slot (from t
calibration event will be ignored and the internal clock
frequency will remain unchanged. If the value (f
not been previously calibrated, it will remain at its default
level.
Synchronization of both Channels
modules, perfect synchronization over a long time can not be
achieved, since both clock signals are independent.
However, when the channels are driven from the external
clock, perfect synchronization can be achieved by
simultaneously setting PWM_en_1=1 and PWM_en_0=1.
The best way to optimize EMC is to use an external clock with
a staggered switch on delay (see
PARALLEL OPERATION
Setting the PARALLEL bit in the GCR register to logic [1] is
mandatory in this case. The improved synchronization of
both transistors will allow an equal current distribution
between both channels. In parallel mode, both output pins
(HS[x]) must be connected, as well as both IN[x] pins, in case
of external control. CONF0 and CONF1 must be set to equal
values.
1- Device Configuration in Parallel mode:
control and Direct Input Control.
• SPI controlled Parallel mode:
PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As
soon as PARALLEL=1, the contents of the corresponding
registers in bank 1 will be replaced by that of bank 0, except
bits D6-D8 of the CONFR_1 register (configuration Open-
Analog Integrated Circuit Device Data
Freescale Semiconductor
When the duration of the negative
When internal clock signals are used to drive the PWM
The channels can be paralleled to drive higher currents.
There are two ways to configure the On/Off control: SPI
The switching configuration is solely defined by the (SI)
SI
CSB
CALR_s
CSB(MIN)
period of channel s
SI command
Internal clock
ignored
Table
t
t
CSB
CSB
to t
CSB
CSB(MAX)
7).
pulse is outside a
PWM(0)
), the
) has
load/Output short-circuited diagnostics). It is recommended
to disable the off-state open-load for the HS1 output. After
setting PARALLEL=1, contents of SO registers in bank 0 are
copied to the registers of bank 1 only when new information
is written in them. Bits OD3, OD4 and OD5 of both
FAULTR_s registers are always reported independently.
• Direct Input mode:
2- Diagnostics in Parallel Mode:
• Open-load in OFF state and - Open-load in ON state:
will independently report failures of the channels according to
the settings of bits D7 and D6 of the CONFR_s register.
• Current sensing:
current sensing modes.
register) is considered. The corresponding bit in the OCR_1
register is copied from that of the OCR_0 register.
• Output shorted to battery:
independently report this fault, according to the settings of bit
D8 of the CONFR_s reg.
3- Protections in Parallel Mode:
• Over-current:
blanking windows of channel 0 are considered.
channels are turned-off. Regardless the order of occurrence
of OC, both OC-bits (OD0) in the FAULT registers are
simultaneously set to logic 1.
• Severe short-circuit:
turned-off and the SC bits (OD1) in both FAULT registers are
simultaneously set to logic 1.
• Over-temperature:
turned-off and both OT bits in the FAULT registers (OD2) are
simultaneously set to logic 1.
• auto-retry:
successive turn-on events on paralleled channels
(RETRYR_0). The counter value in register RETRYR_1
(OD4…OD7) is copied from that in RETRYR_0.
delatched.
The IN0 and IN1 pins must be connected externally.
The Diagnostics in Parallel mode operate as follows:
The OL_ON and OL_OFF bits of both FAULTR registers
Refer to the
Only the Current sense ratio of bank 0 (D5 of the OCR_0
The OS-bit (OD3) of each of both FAULT registers will
-Only the Configuration of over-current thresholds &
-In case over-current (OC) occurs on any channel, both
In case of SC detection on any channel, both channels are
In case of OT detection on any channel, both channels are
Only one 4-bit auto-retry counter specifies the number of
To delatch the channels, only channel 0 needs to be
Table 22
OPERATION AND OPERATING MODES
for a description of the various
FUNCTIONAL DEVICE OPERATION
10XS4200
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