C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 434

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
31.9. Master Mode Unidirectional Data Transfer
A unidirectional SPI master mode DMA transfer will transfer a specified number of bytes out on the MOSI
pin. The MOSI data must be stored in XRAM before initiating the DMA transfers. The SPI1DAT-to-XRAM
peripheral request is not used. Since the DMA does not read the SPI1DAT SFR, the SPI will discard the
MISO data.
A unidirectional transfer only requires one DMA channel to transfer XRAM data to the SPI1DAT SFR. The
DMA interrupt will indicate the completion of the data transfer to the SPI1DAT SFR. When the interrupt
occurs, the DMA has written all of the data to the SPI1DAT SFR, but the SPI has not transmitted the last
byte. Firmware may poll on the SPIBSY bit to determine when the SPI has transmitted the last byte. Firm-
ware should not deassert the NSS pin until after the SPI has transmitted the last byte.
To initiate a master mode unidirectional data transfer:
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1. Configure the SPI1 SFRs normally for Master mode.
2. Configure the desired DMA channel for the XRAM-to-SPI1DAT transfer.
3. Clear the interrupt bit in DMA0INT for the desired channel.
4. Enable the desired channel by setting the corresponding bit in the DMA0EN SFR to initiate the SPI
5. Wait on the DMA interrupt.
6. Clear the DMA enables in the DMA0EN SFR.
7. Clear the DMA interrupts in the DMA0INT SFR.
8. If desired, wait on the SPIBSY bit in SPI1CFG for the last byte transfer to complete.
transfer operation.
a. Enable Master mode by setting bit 6 in SPI1CFG.
b. Configure the clock polarity CKPOL and clock phase CKPHA as desired in SPI1CFG.
c. Configure SPI1CKR for the desired SPI clock rate.
d. Configure the desired 4-wire master or 3-wire master mode in SPI1CN.
e. Enable the SPI by setting bit 0 of SPI1CN.
a. Disable the desired DMA channel by clearing the corresponding bit in DMA0EN.
b. Select the desired DMA channel by writing to DMA0SEL.
c. Configure the selected DMA channel to use the XRAM-to-SPI1DAT XRAM peripheral request by
d. Enable DMA interrupts for the desired channel by setting bit 7 of DMA0NCF.
e. Write 0 to DMA0NMD to disable wrapping.
f.
g. Write the size of the SPI transfer in bytes to DMA0NSZH:L.
h. Clear the address offset SFRs CMA0A0H:L.
i.
j.
writing 0x03 to DMA0NCF.
Write the address for the first byte of master output (MOSI) data to DMA0NBAH:L.
Enable the interrupt on the desired channel by setting the corresponding bit in DMA0INT.
Enable DMA interrupts by setting bit 5 of EIE2.
Rev. 0.5