C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 317

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
25.4. Automatic Pull-Up Resistor Calibration
The Pulse Counter includes an automatic calibration engine which can automatically determine the mini-
mum pull-up current for a particular application. The automatic calibration is especially useful when the
load capacitance of field wiring varies from one installation to another.
The automatic calibration uses one of the Pulse Counter inputs (PC0 or PC1) for calibration. The CAL-
PORT bit in the PC0PCF SFR selects either PC0 or PC1 for calibration. The reed switch on the selected
input should be in the open state to allow the signal to charge during calibration. The calibration engine can
calibrate the pull-ups with the meter connected normally, provided that the reed switch is open during cali-
bration. During calibration, the integrators will ignore the input comparators, and the counters will not be
incremented. Using a 250 µs sample rate and a 32 kHz RTCCLK, the calibration time will be 21 ms (28
tests @ 750 µs each) or shorter depending on the pull up strength selected. The calibration will fail if the
reed switch remains closed during this entire period. If the reed switch is both opened and closed during
the calibration period, the value written into PCCF[4:0] may be larger than what is actually required. The
transition flag in the PC0INT1 can detect when the reed switch opens, and most systems with a wheel
rotation of 10 Hz or slower should have sufficient high time for the calibration to complete before the next
closing of the reed switch. Slowing the sample rate will also increase the calibration time. The same drive
strength will used for both PC0 and PC1.
The example code for the Pulse Counter includes code for managing the automatic calibration engine.
25.5. Sample Rate
The Pulse Counter has a programmable sampling rate. The Pulse Counter samples the state of the reed
switches at discrete time intervals based on the RTC clock. The PC0MD SFR sets the sampling rate. The
system designer should carefully consider the maximum pulse rate for the particular application when set-
ting the sampling rate and debounce time. Sample rates from 250 µs to 2 ms can be selected to either fur-
ther reduce power consumption or work with shorter pulse widths. The slowest sampling rate (2 ms) will
provide the lowest possible power consumption.
25.6. Debounce
Like most mechanical switches, reed switches exhibit switch bouncing that could potentially result in false
counts or quadrature errors. The Pulse Counter includes digital debounce logic using a digital integrator
that can eliminate false counts due to switch bounce. The input of the integrator connects to the Pulse
Counter inputs with the programmable pull-ups. The output connects to the counters.
The debounce integrator has two independent programmable thresholds: one for the rising edge
(Debounce High) and one for the falling edge (Debounce Low). The PC0DCH (PC0 Debounce Config
High) SFR sets the threshold for the rising edge. This SFR sets the number of cumulative high samples
required to output a logic high to the counter. The PC0DCL (PC0 Debounce Config Low) SFR sets the
threshold for the falling edge. This SFR sets the number of cumulative high samples required to output a
logic low to the counter.
Note that the debounce does count consecutive samples. Requiring consecutive samples would be sus-
ceptible to noise. The digital integrator inherently filters out noise.
The system designer should carefully consider the maximum anticipated counter frequency and duty-cycle
when setting the debounce time. If the debounce configuration is set too large, the Pulse Counter will not
count short pulses. The debounce-high configuration should be set to less than one-half the minimum
input pulse high-time. Similarly, the debounce-low configuration should be set to less than one-half the
minimum input pulse low-time.
The Debounce Timing diagram (Figure 25.4) illustrates the operation of the debounce integrator. The top
waveform is the representation of the reed switch (high: open, low: closed) which shows some random
switch bounce. The bottom waveform is the final signal that goes into the counter which has the switch
bounce removed. Based on the actual reed switch used and sample rate, the switch bounce time may
appear shorter in duration than the example in Figure 25.4. The second waveform is the pull-up resistor
Rev. 0.5
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