C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 178

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
14.1.3. Configuration sfrs
The AES Module has two configuration sfrs. The AES0BCFG sfr is used to configure the AES core. Bits 0
and 1 are used to select the Key size. The AES core supports 128-bit, 192-bit and 256-bit encryption. Bit 2
selects encrypt or decrypt. The AES enable bit (bit 3) is used to enable the AES module and start and new
encryption operation. The AES DONE bit (bit 5) is the AES interrupt flag that signals a block of data has
been completely encrypted or decrypted and is ready to be read from the AES0YOUT sfr. Note that the
AES DONE interrupt is not normally used when the AES module is used with the DMA. Instead the DMA
interrupt is used to signal that the encrypted or decrypted data has been transferred completely to memory.
The DMA done interrupt is normally only used with direct sfr access.
The AES0DCFG sfr is used to select the data path for the AES module. Bits 0 through 2 are used to select
the input and output multiplexer configuration. The AES data path should be configured prior to initiating a
new encryption or decryption operation.
14.1.4. Input Multiplexer
The input multiplexer is used to select either the contents of the AES0BIN sfr or the contents of the
AES0BIN sfr exclusive ORed with the contents of the AES0XIN sfr. The exclusive OR input data path pro-
vides support for CBC encryption.
14.1.5. Output Multiplexer
The output multiplexer selects the data source for the AES0YOUT sfr. The three possible sources are the
AES Core data output, the AES Core Key output, and the AES core data output exclusive ORed with the
AES0XIN sfr.
The AES core data output is used for simple encryption and decryption.
The exclusive OR output data path provides support for CBC mode decryption and CTR mode encryp-
tion/decryption. The AES0XIN is the source for both input and output exclusive OR data. When the
AES0XIN is used with the input exclusive OR data path, the AEXIN data is written in sequence with the
AES0BIN data. When used with the output XRO data path, the AES0XIN data is written after the encryp-
tion or decryption operation is complete.
The Key output is used to generate an inverse key. To generate a decryption key from an encryption key,
the AES core should be configured for an encryption operation. To generate an encryption key from a
decryption key, the AES core should be configured for a decryption operation.
14.1.6. Internal State Machine
The AES Module has an internal state machine that manages the data flow. The internal state machine
accommodated the two different usage scenarios. When using the DMA, the internal state machine will
send peripheral requests to the DMA requesting the DMA to transfer data from xram to the AES module
input sfrs. Upon the completion of one block of data, the AES module will send peripheral requests
requesting data to be transferred from the AES0YOUT sfr to xram. These peripheral requests and are
managed by the internal state machine.
When not using the DMA, data must be written and read in a specific order. The DMA state machine will
advance with each byte written or read.
The internal state machine may be reset by clearing the enable bit in the AESBGFG sfr. Clearing the
enable bit before encryption or decryption operation will ensure that the state machine starts at the proper
starting state.
When encrypting or decrypting multiple blocks it is not necessary to disable the AES module between
blocks, as long as the proper sequence of events is obeyed.
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